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參數(shù)資料
| 型號： | HMS30C7202N |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Highly-intergrated MPU |
| 中文描述： | 高intergrated微處理器 |
| 文件頁數(shù)： | 86/179頁 |
| 文件大?。?/td> | 2127K |
| 代理商： | HMS30C7202N |
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HMS30C7202N
2004 MagnaChip Semiconductor Ltd. All Rights Reserved. Version 1.1
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interrupt when SmartMedia comes back to ready mode.
9.3.2.4
SMC Data Read Register (SMCDATR)
0x8001.600C
17
16
31
N * (SMCADR + 3)’s Byte Data
15
14
13
N * (SMCADR + 1)’s Byte Data
30
29
28
27
26
25
24
23
N * (SMCADR + 2)’s Byte Data
7
6
5
N * SMCADR’s Byte Data
22
21
20
19
18
12
11
10
9
8
4
3
2
1
0
Bits
31:0
Type
R
Function
Four byte data read from SmartMedia is stored in this register. SMC controller receives a byte
data from SmartMedia and stores it into 4 byte internal buffer to create 32bit data. First read
byte data is stored at least significant byte and fourth byte data is stored at most significant
byte of buffer. Host controller or DMA controller read this register to get 4 byte data at a time.
This SMC controller reads a whole page at a single read transaction, so it requires 132 times
consecutive reading. A page reading process is as follows:
1. Set SMCCMD to xxxx00yyh (xxxx can be unique ID if redundant area accessed, yy is don’t
care. Only 00h command is valid. No 01h or 50h command supported) and then set
SMCADR to target page address.
2. SMC controller will access SmartMedia with given command and address.
3. Interrupt (or DMA interrupt according to interrupt mode setting) will be generated after first
four byte read. Like writing process, reading process reads a whole 528 byte in a page at a
single transaction, so interrupt will be 132 times.
Against to write operation, there is no read finish interrupt because we can count the number
of read transfers in software or can get the total access word size from BYTE COUNT of
SMCSTAT.
9.3.2.5
SMC Configuration Register (SMCCONF)
0x8001.6010
31
POWER
ENABLE
6
SAFE
MARGIN
5
SMC
ENABLE
4
CONT
PAGE EN
3
2
1
UNIQUE
ID EN
0
BIG CARD
ENABLE
INTR EN
DMA EN
Bits
31
Type
R/W
Function
Power on bit. To activate SMC controller, set this bit. Reset will fall the controller into the deep
sleep mode.
Reserved. Keep these bits to zero.
Safe margin enable bit. In normal mode, chip select signal changes simultaneously with read
enable and write enable signals. But when this bit set, the duration of read and write enable
signal applied to SmartMedia is reduced by 1 automatically. By enabling this, the rising edge
of read and write enable signal will be earlier than the rising edge of chip enable, which
guarantees latching data safely.
SMC controller enable bit. Reset this bit will make SMC controller stay in standby mode. No
interrupt generated, no action occurred.
Continuous page read enable. If this bit set, then multi-page can be accessed in a single
command and address setting. Usually DMA controller accesses multiple pages with a start
address and a predefined size. Setting DMA access size in SMCTIME and enabling this bit
will automatically read or write SmartMedia with DMA mode.
Interrupt enable. After reading a word or before writing a word, the interrupt bit of SMCSTAT
will be set and interrupt will occur if INTR EN is enabled. If this bit is disabled, software must
poll the interrupt flag of SMCSTAT to know the occurrence of an interrupt. After writing a
whole page (or pages when CONT PAGE EN is enabled) to SmartMedia, write finish interrupt
will also be generated to notice that the SmartMedia complete the write operation
successfully.
DMA enable. If set, all interrupt during read or write data will be sent to DMA controller.
However, write finish interrupt is a still normal interrupt. To minimize CPU burden and to
maximize BUS utilization, enabling both interrupt and DMA mode together is recommended.
Redundant page enable. When use SmartMedia with unique ID and want to access
redundant page area, set high. This bit cannot be cleared automatically, so in order to read
30:7
6
-
R/W
5
R/W
4
R/W
3
R/W
2
R/W
1
R/W
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