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參數(shù)資料
| 型號： | HMS30C7202N |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Highly-intergrated MPU |
| 中文描述： | 高intergrated微處理器 |
| 文件頁數(shù)： | 125/179頁 |
| 文件大?。?/td> | 2127K |
| 代理商： | HMS30C7202N |
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HMS30C7202N
2004 MagnaChip Semiconductor Ltd. All Rights Reserved. Version 1.1
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1.
transmitted serially.
2.
If data signal is pulled low by the external devices and clock signal’s negative edge is
detected, a receive sequence begins and data is clocked into PSDATA register.
At the end of transmission, transmit interrupt will occur. By reading PSSTAT status register will
reveal the data is transmitted properly. Reading PSSTAT also de-asserts transmit interrupt
request.
PS/2 controller usually remains in receive data mode if no data is transmitting. The controller
automatically receives data from external device and generates receive interrupt. By just
reading PSDATA register the data will be acquired and the receive interrupt will be cleared.
If data is written to the PSDATA register, a transmit sequence is initiated and the data is
10.5.2.2
PSSTAT
0x8002.C004
6
PARITY
5
DATA IN
4
CLK IN
3
RX BUSY
2
RX FULL
1
TX BUSY
0
TX EMPTY
Bits
7
6
5
4
3
2
1
0
Type
-
R/O
R/O
R/O
R/O
R/O
R/O
R/O
Function
Reserved. Always Zero
The parity bit of the last received data byte
Double synchronized value of the current PSDAT being received/transmitted
Double synchronized value of the current PSCLK being received/transmitted
This bit indicates that the PS/2 controller is currently receiving data or not
This bit indicates that the a data is received and ready to be read
This bit indicates that the PS/2 controller is currently transmitting data or not
This bit indicates that the transmit register is empty and ready to transmit
10.5.2.3
PSCONF
0x8002.C008
6
5
FORCE
DAT LOW
4
FORCE
CLK LOW
3
RX
INTREN
2
TX
INTREN
0
LCE
ENABLE
Bits
7
6
Type
-
R/W
Function
Reserved
L
ine
C
ontrol detection
E
nable bit. If set, PS/2 controller checks the line control bit from
external device following by STOP bit. Otherwise PS/2 controller skips checking line control
bit and proceeds to next operation. Default value is zero. Most PS/2 compatible device
supports line control bit mechanism. But there are some devices that don’t support line control
bit. To handle such device, PS/2 controller can skip line control bit detection by resetting this
bit.
When set, PSDAT output is forced LOW regardless of the current state of the PS/2 control
logic. This mode can be used as manual communication with external device.
When set, PSCLK output is forced LOW regardless of the current state of the PS/2 control
logic.
Enable receiver interrupt. To set means enable interrupt. Receiver interrupt is generated
whenever PS/2 controller finishes receiving a byte data from external device. Except when
transmit data, PS/2 controller goes in receive mode automatically. If receiver interrupt is
disabled, PS/2 controller doesn’t notify a data received. So polling PSINTR interrupt register
is needed.
Enable transmitter interrupt. To set means enable interrupt. Transmitter interrupt is generated
whenever PS/2 controller completes to transmit a byte data to external device. If transmitter
interrupt is disabled then poll status register to know that the transmitting transaction is
completed or poll interrupt register transmitter interrupt is generated.
Reserved
When reset, PS/2 controller is disabled and gets into deep sleep mode. When set, enabled.
To activate PS/2 controller,, first set proper parameters of timing registers and then set this bit.
As soon as this bit is enabled, PS/2 controller goes into receive mode by default.
5
R/W
4
R/W
3
R/W
2
R/W
1
0
-
R/W
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