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參數(shù)資料
| 型號： | HMS30C7202N |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Highly-intergrated MPU |
| 中文描述： | 高intergrated微處理器 |
| 文件頁數(shù)： | 63/179頁 |
| 文件大小： | 2127K |
| 代理商： | HMS30C7202N |
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HMS30C7202N
2004 MagnaChip Semiconductor Ltd. All Rights Reserved. Version 1.1
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disabled (LcdEn = 0) and the frame that is current active finishes being output to the LCD's
data pins. It is cleared by writing the base address (LcdDBAR) or enabling the LCD, or, by
writing "1" to the LDone bit of the Status Register. When the LCD is disabled by clearing the
LCD enable bit (LcdEn=0) in LcdControl, the LCD allows the current frame to complete before
it is disabled. After the last set of pixels is clocked out onto the LCD's data pins by the pixel
clock, the LCD is disabled and Done is set.
Vertical compare interrupt
This bit is set when the Lcd timing generator reaches the vertical region programmed in the
Video Control Register. This bit is "sticky", meaning it remains set until it is cleared by writing
a "1" to this bit
LCD Next base address update status/mask/interrupt bit
The LCD Next Frame (LNext) is a read-only status bit that is set after the contents of the LCD
DMA base address register are transferred to the LCD DMA current address register at the
start of frame, and it is cleared when the LCD DMA base address register is written.
FIFO underflow status/mask/interrupt bit
The LCD FIFO underflow (LFUF) status bit is set when the LCD FIFO under-runs. The status
bit is "sticky", meaning it remains set after the FIFO is no longer underrunning. The status bit
is cleared by writing a `1' to this bit.
2
R/W
1
R
0
R/W
8.2.3
LCD DMA Base Address Register
The LCD DMA base address register (LcdDBAR) is a read/write register used to specify the base address of
the off-chip frame buffer for the LCD. Addresses programmed in the base address register must be aligned on
sixteen-word boundaries, thus the least significant six bits (LcdDBAR [5:0]) must always be written with zeros.
Only 26 bits of the register are valid (including the LS 6 bits which must be zero), because LCD DMA is only
allowed from SDRAM.
The 26 bits address range allows the LCD DMA to access any address within the SDRAM. The upper address
lines are not needed, because these are the address lines used to select which device is accessed, but the
LCD always accesses SDRAM. The user must initialize the base address register before enabling the LCD,
and may also write a new value to it while the LCD is enabled to allow a new frame buffer to be used for the
next frame. The user can change the state of LcdDBAR while the LCD controller is active, after the Next
Frame (Next) status bit is set within the LCD's status register that generates an interrupt request. This status
bit indicates that the value in the base address pointer has been transferred to the current address pointer
register and that it is safe to write a new base address value. This allows double-buffered video to be
implemented if required.
0x80010010
Bits
31:26
25:6
Type
-
R/W
Function
Reserved. Keep these bits zero
LcdDBAR
: LCD DMA Channel Base Address Pointer
16-word aligned base address in SDRAM of the frame buffer within off-chip memory.
Reserved. Keep these bits zero
5:0
-
8.2.4
LCD DMA Channel Current Address Register
This read-only register allows the processor to read the current value of the LCD DMA channel current
address register. This is not something that would normally be done, but it allows additional test observability.
Its value cannot be expected to be exact, it could change at an moment. However, its contents can be read to
determine the approximate line that the LCD controller is currently displaying and driving out to the display
0x80010014
Bits
31:26
25:6
Type
-
R/W
Function
Reserved. Keep these bits zero
LcdDCAR
: LCD DMA Channel Current Address Pointer
16-word aligned current address pointer to data in SDRAM frame buffer currently being
displayed
Reserved. Keep these bits zero
5:0
-
8.2.5
LCD Timing 0 Register
LCD Timing 0 Register (LcdTiming0) controls horizontal LCD timing. See 8.6.2 Pixel Clock Divider (PCD) on
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