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參數(shù)資料
| 型號： | HMS30C7202N |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Highly-intergrated MPU |
| 中文描述： | 高intergrated微處理器 |
| 文件頁數(shù)： | 69/179頁 |
| 文件大小： | 2127K |
| 代理商： | HMS30C7202N |
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HMS30C7202N
2004 MagnaChip Semiconductor Ltd. All Rights Reserved. Version 1.1
- 64 -
9
FAST AMBA PERIPHERALS
9.1
DMA Controller
This chip includes a three-channel direct memory access controller (DMAC). High-speed transfers between
peripheral devices and the SDRAM can be controlled by the DMAC instead of the CPU core. Transfers using
addresses other than SDRAM will produce unpredictable results.
Features
z
Three Channels.
z
Max Transfer rate: 133MB/s.
z
Max Buffer size: 16383.
z
Address mode: Single(SDRAM) address is supported.
z
Channel function: Transfer modes are different in each channel.
i.
Channel 0:
Dedicated to the sound interface controller. This channel has a source address reload
function. The memory space of the sound I/O device consists of a double buffer. The
sound interface uses exception bus mode and word access. The channel performs only
DMA transfers for transmitting data (transfers from SDRAM to the sound interface).
ii.
Channel 1:
Dedicated to the SMC/MMC interface block. The channel uses exception bus mode and
word access. It controls DMA transfers for both transmitting (from SDRAM) and receiving
(to SDRAM). Word is the only supported transfer size. Correct DMA operation of this
channel is guaranteed only if the SDRAM write buffer is enabled and LCD operation is
disabled. Otherwise it will produce unpredictable results.
iii.
Channel 2:
Used by external IO device. The channel supports both exception and burst bus modes.
Transfer sizes of byte, half word (16 bits) and word are all supported.
z
Channel priority: Configured by register setting.
z
Interrupt request: The DMAC interrupt request can be triggered by each channel whenever the DMA
transfer is completed by buffer size. Since only one interrupt ID is assigned to the DMAC,
the interrupt flag register (FLAGR) maintains the information on which DMA channel
requested the interrupt.
z
The channel 2 should not be enabled with either of the other channels at the same time.
9.1.1
External Signals
Pin Name
nDMAREQ
nDMAACK
Type
I
O
Description
DMA request input signal from external device (level sensitive, active Low)
DMA acknowledge output signal to external Device.
9.1.2
Registers
Address
0x8000.4000
Name
ADR0
Width
32
Default
0x0
Description
Write: Start address of the first buffer of Channel 0
Read: Current address of the first buffer of Channel 0
Write: Start address of the second buffer of Channel 0
Read: Current address of the second buffer of Channel 0
Write: Size of the first buffer of Channel 0 (in words)
Read: Number of words in the first buffer of Channel 0
which remain to be transferred
Write: Size of the second buffer of Channel 0 (in words)
Read: Number of words in the second buffer of Channel
0 which remain to be transferred
Channel 0 control
Write: Start address of Channel 1 buffer
Read: Current address of Channel 1 buffer
Write: Size of Channel 1 buffer (in words)
Read: Number of words in Channel 1 buffer which
remain to be transferred
0x8000.4004
ASR
32
0x0
0x8000.4008
TNR0
14
0x3FFF
0x8000.400C
TSR
14
0x3FFF
0x8000.4010
0x8000.4014
CCR0
ADR1
4
32
0x0
0x0
0x8000.4018
TNR1
14
0x3FFF
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