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參數(shù)資料
| 型號： | HMS30C7202N |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Highly-intergrated MPU |
| 中文描述： | 高intergrated微處理器 |
| 文件頁數(shù)： | 37/179頁 |
| 文件大?。?/td> | 2127K |
| 代理商： | HMS30C7202N |
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HMS30C7202N
2004 MagnaChip Semiconductor Ltd. All Rights Reserved. Version 1.1
- 32 -
4
R/w
OnEvt (debounced)
When reads, 0 = No On key event since last cleared; 1 = On key event since last cleared
When writes, OnEvt Interrupt Clear. Writing a `1' to this bit clears a pending interrupt bit.
PLLLock3
When reads,
0 = System PLL has been locked since last cleared
1 = System PLL has fallen out of lock since last cleared
When writes, writing a `1' to this bit causes the PLL3 Unlock event flag to be cleared.
PLLLock2
When reads,
0 = Comms PLL has been locked since last cleared
1 = Comms PLL has fallen out of lock since last cleared
When writes, writing a `1' to this bit causes the PLL2 Unlock event flag to be cleared.
PLLLock1
When reads,
0= LCD PLL has been locked since last cleared
1= LCD PLL has fallen out of lock since last cleared
When writes, writing a `1' to this bit causes the PLL1 Unlock event flag to be cleared.
PORStatus
When reads, 0 = No POR since last cleared; 1 = POR since last cleared
When writes, writing a `1' to this bit causes the nPOR event flag to be cleared.
3
R/w
2
R/w
1
R/w
0
R/w
5.3.4
PMU Clock Control Register (PMUCLK)
This register is used to control the frequency of PLL3, the system clock PLL and PLL1, the LCD clock. Six bits
are defined which control the frequency of FCLK, and a further bit is used to control the frequency of PLL1, the
LCD clock. The Default (Power on Reset) value for this register is 0x2126.
0x80001028
15
PLL2
ENABLE
7
14
PLL1
ENABLE
6
PLL3
FREQ
UPDATE
13
12
11
10
9
8
PLL1 FREQ
5
4
3
2
1
0
PLL3
MUTE
PLL3 FREQ
Bits
31:16
15
Type
-
R/W
Function
Reserved
Set for PLL2 enable. Output will be gated until PLL2 Lock Detect (LD) is received. Reset for
disable PLL2
Set for PLL1 enable. Output will be gated until PLL1 Lock Detect (LD) is received. Reset for
disable PLL1
Same with bit [5:0]. But output clock frequency will be half of PLL3 – default 30.4128 MHz
Reset: PLL3 is muted when Lock detect = 0 (default)
Set: PLL3 only muted after nPOR or nRESET. Subsequent unlock condition does not mute
the clock. Allows dynamic changes to the clock frequency without halting execution. Care: this
only will be legal if PLL3 is under-damped (i.e. will not exhibit overshoot in its lock behavior).
Reset: PLL3 frequency control frequency is only updated when PMU exits DEEP SLEEP
mode (default)
Set: PLL3 frequency control frequency is updated instantaneously
Value Frequency Value Frequency
0x1B 49.7664 MHz 0x25 68.1984 MHz
0x1C 51.6096 MHz 0x26 70.0416 MHz - default
0x1D 53.4528 MHz 0x27 71.8848 MHz
0x1E 55.2960 MHz 0x28 73.7280 MHz
0x1F 57.1392 MHz 0x29 75.5712 MHz
0x20 58.9824 MHz 0x2A 77.4144 MHz
0x21 60.8256 MHz 0x2B 79.2576 MHz
14
R/W
13:8
7
R/W
R/W
6
R/W
5:0
R/W
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