參數(shù)資料
型號： HMS30C7202N
廠商： Electronic Theatre Controls, Inc.
英文描述： Highly-intergrated MPU
中文描述： 高intergrated微處理器
文件頁數(shù)： 6/179頁
文件大?。?/td> 2127K
代理商： HMS30C7202N
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HMS30C7202N
2004 MagnaChip Semiconductor Ltd. All Rights Reserved. Version 1.1
- 1 -
TABLE OF CONTENTS
1
ARCHITECTURAL OVERVIEW ...........................................................................................................................9
1.1
1.2
1.3
1.4
P
ROCESSOR
............................................................................................................................................................9
V
IDEO
...................................................................................................................................................................9
M
EMORY
...............................................................................................................................................................9
I
NTERNAL
B
US
S
TRUCTURE
....................................................................................................................................9
1.4.1
ASB...............................................................................................................................................................9
1.4.2
Video bus ......................................................................................................................................................9
1.4.3
APB ..............................................................................................................................................................9
1.5
SDRAM
C
ONTROLLER
........................................................................................................................................10
1.6
P
ERIPHERAL
DMA...............................................................................................................................................10
1.6.1
Overview.....................................................................................................................................................10
1.6.2
Transfer sizes..............................................................................................................................................10
1.6.3
Fly-by .........................................................................................................................................................10
1.6.4
Timing......................................................................................................................................................... 11
1.6.5
Sound output............................................................................................................................................... 11
1.7
P
ERIPHERALS
....................................................................................................................................................... 11
1.8
P
OWER MANAGEMENT
......................................................................................................................................... 11
1.8.1
Clock gating ...............................................................................................................................................12
1.8.2
PMU...........................................................................................................................................................12
1.9
T
EST AND DEBUG
.................................................................................................................................................12
2
PIN DESCRIPTION ................................................................................................................................................13
2.1
256-P
IN
D
IAGRAM
...............................................................................................................................................13
2.1.1
MQFP Type ................................................................................................................................................13
2.1.2
FBGA Type .................................................................................................................................................15
2.2
P
IN
D
ESCRIPTIONS
...............................................................................................................................................17
2.2.1
External Signal Functions..........................................................................................................................17
2.2.2
Multiple Function Pins...............................................................................................................................20
2.2.2.1
PORT A ..................................................................................................................................................20
2.2.2.2
PORT B ..................................................................................................................................................20
2.2.2.3
PORT C ..................................................................................................................................................21
2.2.2.4
PORT D..................................................................................................................................................21
2.2.2.5
PORT E...................................................................................................................................................22
2.2.2.6
USB Transceiver Test & Analog Test .....................................................................................................23
2.2.2.7
DMA.......................................................................................................................................................23
2.2.2.8
Inverter Chain.........................................................................................................................................23
3
ARM720T MACROCELL.......................................................................................................................................24
3.1
ARM720T
M
ACROCELL
......................................................................................................................................24
4
MEMORY MAP.......................................................................................................................................................25
5
PMU & PLL..............................................................................................................................................................27
5.1
5.2
B
LOCK
F
UNCTIONS
..............................................................................................................................................27
P
OWER MANAGEMENT
.........................................................................................................................................28
5.2.1
State Diagram.............................................................................................................................................28
5.2.2
Power management states..........................................................................................................................28
5.2.3
Wake-up Debounce and Interrupt...............................................................................................................29
5.3
R
EGISTERS
...........................................................................................................................................................30
5.3.1
PMU Mode Register (PMUMODE) ...........................................................................................................30
5.3.2
PMU ID Register (PMUID)........................................................................................................................30
5.3.3
PMU Reset /PLL Status Register (PMUSTAT)............................................................................................30
5.3.4
PMU Clock Control Register (PMUCLK)..................................................................................................32
5.3.5
PMU Debounce Counter Test Register (PMUDBCT).................................................................................33
5.3.6
PMU PLL Test Register (PMUPLLTR).......................................................................................................33
5.4
T
IMINGS
..............................................................................................................................................................34
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