參數(shù)資料
型號: FW82439TX
英文描述: Controller Miscellaneous - Datasheet Reference
中文描述: 控制器雜項-數(shù)據(jù)表參考
文件頁數(shù): 70/102頁
文件大?。?/td> 759K
代理商: FW82439TX
Extended Temperature 82439TX (MTXC) Datasheet
70
PRELIMINARY
Table 22. PCI Commands
C/BE#
Command
Target Support
Initiator Support
1110
Memory Read Line
As Memory Read
NO
1111
Memory Write and Invalidate
As Memory Write
NO
4.8.
System Arbitration
The MTXC’s PCI Bus Arbiter allows PCI peer-to-peer traffic concurrent with CPU main memory/second level
cache cycles. The arbiter supports five PCI masters. REQ[3:0]#/GNT[3:0]# are used by PCI masters other
than the PCI-to-ISA expansion bridge (PIIX4). PHLD#/PHLDA# are the arbitration request/grant signals for
the PIIX4 and provide guaranteed access time capability for ISA masters. PHLD#/PHLDA# also optimize
system performance based on the PIIX4 known policies.
Arbiter
PHLD#
REQ0#
REQ1#
REQ2#
REQ3#
PHLDA#
GNT0#
GNT1#
GNT2#
GNT3#
mtxc_06
Figure 10. PCI Arbiter
4.8.1.
PRIORITY SCHEME AND BUS GRANT
The highest priority requester is determined by a fixed order queue together with a highest priority pointer.
Although the priority ring is fixed, the highest priority pointer moves to determine which PCI agent is at the top
(and bottom) of the queue. The arbiter counts three grant assertions to requesters different than the one it is
currently granting (and all grants within MTT are collapsed to one) to decide when it’s time to let the host in.
The grant signals (GNTx#) are normally negated after recognition of FRAME# assertion, or 16 PCLKs from
grant assertion, if no cycle has started.
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