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參數(shù)資料
| 型號： | FW82439TX |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項-數(shù)據(jù)表參考 |
| 文件頁數(shù)： | 14/102頁 |
| 文件大?。?/td> | 759K |
| 代理商： | FW82439TX |
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Extended Temperature 82439TX (MTXC) Datasheet
14
PRELIMINARY
2.1.4.
PCI INTERFACE
Name
Type
Description
AD[31:0]
I/O
3.3/5V
Address/Data.
The standard PCI address and data lines. Address is driven with
FRAME# assertion, data is driven or received in following clocks.
C/BE[3:0]#
I/O
3.3/5V
Command/Byte Enable.
The command is driven with FRAME# assertion, byte
enables corresponding to supplied or requested data is driven on following clocks.
FRAME#
I/O
3.3/5V
Frame.
Assertion indicates the address phase of a PCI transfer. Negation
indicates that one more data transfer is desired by the cycle initiator.
DEVSEL#
I/O
3.3/5V
Device Select.
This signal is driven by the MTXC when a PCI initiator is
attempting to access DRAM. DEVSEL# is asserted at medium decode time.
IRDY#
I/O
3.3/5V
Initiator Ready.
Asserted when the initiator is ready for a data transfer.
TRDY#
I/O
3.3/5V
Target Ready.
Asserted when the target is ready for a data transfer.
STOP#
I/O
3.3/5V
Stop.
Asserted by the target to request the master to stop the current transaction.
LOCK#
I/O
3.3/5V
Lock.
Used to establish, maintain, and release resource locks on PCI.
REQ[3:0]#
I
3.3/5V
PCI Request.
PCI master requests for PCI bus.
GNT[3:0]#
O
3.3V
PCI Grant.
Permission is given to the master to use PCI.
PHLD#
I
3.3/5V
PCI Hold.
This signal comes from the expansion bridge. It is the bridge request
for PCI. The MTXC will drain the DRAM write buffers, drain the CPU-to-PCI
posting buffers, and acquire the host bus before granting via PHLDA#.
PHLDA#
O
3.3V
PCI Hold Acknowledge.
This signal is driven by the MTXC to grant PCI to the
expansion bridge. PHLDA# protocol has been modified to include support for
passive release.
PAR
I/O
3.3/5V
Parity.
A single parity bit is provided over AD[31:0] and C/BE[3:0]. This signal
should be pulled high through a weak external pull-up resistor.
CLKRUN#
I/O
3.3/5V
CLOCK RUN.
An open drain output and also an input. MTXC requests the central
resource (PIIX4) to start, or maintain the PCI clock by the assertion of CLKRUN#.
MTXC will tri-state CLKRUN# upon negation of reset (since CLK is running upon
negation of reset). External pull-up is required. Note: This signal should be
connected to the PIIX4 CLKRUN# pin. However, if it is left as a no connect on the
MTXC, it must be pulled low through a 100
(pull-down resistor.
RST#
I
3.3/5V
Reset.
When asserted this signal asynchronously resets the MTXC. The PCI
signals also tri-state compliant to PCI Rev 2.0 and 2.1 specifications.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| FW82439TX S L28T | 制造商:Intel 功能描述:System Controller 324-Pin BGA |
| FW82439TX S L3BT | 制造商:Intel 功能描述:System Controller |
| FW82439TX S L28T | 制造商:Intel 功能描述: |
| FW82439TX S L3BT | 制造商:Intel 功能描述:System Controller |
| FW82439TXSL28T | 功能描述:IC 82439TX SYS CTRL MTXC 324BGA RoHS:否 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
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