參數(shù)資料
型號(hào)： FW82439TX
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項(xiàng)-數(shù)據(jù)表參考
文件頁數(shù)： 36/102頁
文件大?。?/td> 759K
代理商： FW82439TX
Extended Temperature 82439TX (MTXC) Datasheet
36
PRELIMINARY
3.1.20.
DRAMT
DRAM TIMING REGISTER
Address Offset:
Default Value:
Access:
58h
00h
Read/Write
This 8-bit register controls main memory DRAM timings. For SDRAM specific timing control, see the
SDRAMC timing register definition.
Bit
Description
7
Reserved.
6:5
DRAM Read Burst Timing (DRBT).
The DRAM read burst timings are controlled by the DRBT
field. Slower rates may be required in certain system designs to support loose layouts or slower
memories. Most system designs will be able to use one of the faster burst mode timings. The
timing used depends on the type of DRAM on a per-bank basis, as indicated by the DRT register.
DRBT
00
01
10
11
EDO Burst Rate
x444
x333
x222
Reserved
FPM Burst Rate
x444
x444
x333
Reserved
4:3
DRAM Write Burst Timing (DWBT).
The DRAM write burst timings are controlled by the DWBT
field. Slower rates may be required in certain system designs to support loose layouts or slower
memories. Most system designs will be able to use one of the faster burst mode timings.
DWBT
EDO/FPM Burst Rate
00
x444
01
x333
DWBT
10
11
EDO/FPM Burst Rate
x222
Reserved
2
Reserved.
1:0
DRAM Leadoff Timing (DLT)
.
The DRAM leadoff timings are controlled by the DLT bits. Slower
leadoffs may be required in certain system designs to support loose layouts or slower memories.
The Row Miss leadoff timings are summarized below for EDO/FPM reads and writes.
Changing DLT affects the Row Miss and Page Miss timings only (e.g., DLT=01 is one clock faster
than DLT=00 on Row Miss and Page Miss timings). These bit control MA setup to CAS#
assertion.
DLT does not affect page hit timings. Thus, DLT=00 or DLT=01 has same page hit timings for
reads and writes (e.g., for reads, it would be 10-3=7 clocks for DLT=00 or DLT=01)
DLT
Read Leadoff
Write Leadoff
RAS# Precharge
00
11
7
01
10
6
10
11
7
11
10
6
SLD and FELO bits have cumulative effect on the leadoff timings. The above leadoff represent
timings with SLD=1 and FELO=0.
RAS-to-CAS Delay
4
3
4
3
3
3
4
4
相關(guān)PDF資料
PDF描述
FW82815 Controller Miscellaneous - Datasheet Reference
FWA-25A10F Fuse
FWA-30A10F Fuse
FWA-35A21F Fuse
FWA-40A21F Fuse
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
FW82439TX S L28T 制造商:Intel 功能描述:System Controller 324-Pin BGA
FW82439TX S L3BT 制造商:Intel 功能描述:System Controller
FW82439TX S L28T 制造商:Intel 功能描述:
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