參數(shù)資料
型號(hào)： FW82439TX
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項(xiàng)-數(shù)據(jù)表參考
文件頁(yè)數(shù)： 39/102頁(yè)
文件大?。?/td> 759K
代理商： FW82439TX
Extended Temperature 82439TX (MTXC) Datasheet
39
PRELIMINARY
Table 7. PAM Register and Associated Memory Segments
PAM Reg.
Attribute Bits
Memory Segment
Comments
Offset
PAM5[7:4]
R
CE
WE
RE
0E4000h – 0E7FFFh
BIOS Extension
5Eh
PAM6[3:0]
R
CE
WE
RE
0E8000h – 0EBFFFh
BIOS Extension
5Fh
PAM6[7:4]
R
CE
WE
RE
0EC000h – 0EFFFFh
BIOS Extension
5Fh
NOTES:
The CE bit should not be changed while the L2 cache is enabled.
DOS Application Area (00000h–9FFFh)
Read, write, and cacheability attributes are always enabled and are not programmable for the 0
–
640-Kbytes
DOS application region.
Video Buffer Area (A0000h–BFFFFh)
This 128-Kbytes area is not controlled by attribute bits. CPU-initiated cycles in this region are always
forwarded to PCI for termination. This area is not cacheable.
Expansion Area (C0000h–DFFFFh)
This 128-Kbytes area is divided into eight 16-Kbytes segments. Each segment can be assigned one of four
Read/Write states: read-only, write-only, read/write, or disabled Memory that is disabled is not remapped.
Cacheability status can also be specified for each segment.
Extended System BIOS Area (E0000h–EFFFFh)
This 64-Kbytes area is divided into four 16-Kbytes segments. Each segment can be assigned independent
cacheability, read, and write attributes. Memory segments that are disabled are not remapped elsewhere.
System BIOS Area (F0000h–FFFFFh)
This area is a single 64-Kbytes segment. This segment can be assigned cacheability, read, and write
attributes. When disabled, this segment is not remapped.
Extended Memory Area (100000h–FFFFFFFFh)
The extended memory area can be split into several parts:
Flash BIOS area from
4 Gbytes to 4 Gbytes–512 Kbytes (aliased on ISA at 16 Mbytes–15.5 Mbytes)
DRAM Memory from 1 Mbytes to a maximum of 512 Mbytes
PCI Memory space from the top of DRAM to 4 Gbytes–512 Kbytes
On power-up or reset the CPU vectors to the Flash BIOS area, mapped in the range of 4 Gbytes to 4
Gbytes–512 Kbytes. This area is physically mapped on the expansion bus. Since these addresses are in the
upper 4-Gbytes range, the request is directed to PCI.
The DRAM memory space can occupy extended memory from a minimum of 1 Mbytes up to 256 Mbytes.
This memory is cacheable.
PCI memory space from the top of main memory to 4 Gbytes is always non-cacheable.
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