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| 型號： | FW82439TX |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項-數(shù)據(jù)表參考 |
| 文件頁數(shù)： | 20/102頁 |
| 文件大小： | 759K |
| 代理商： | FW82439TX |
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Extended Temperature 82439TX (MTXC) Datasheet
20
PRELIMINARY
3.0.
REGISTER DESCRIPTION
The MTXC contains two sets of software accessible registers (I/O Mapped and PCI configuration registers),
accessed via the Host CPU I/O address space. The I/O mapped registers control access to PCI configuration
space. Configuration registers residing in PCI configuration space used to specify PCI configuration, DRAM
configuration, cache configuration, operating parameters and optional system features.
The MTXC internal registers (both I/O Mapped and PCI Configuration registers) are only accessible by the
Host CPU and cannot be accessed by PCI masters. The registers can be accessed as Byte, Word (16-bit), or
DWord (32-bit) quantities, with the exception of CONFADD, which can only be accessed as a DWord. All
multi-byte numeric fields use “l(fā)ittle-endian” ordering (i.e., lower addresses contain the least significant parts of
the field). The following nomenclature is used for access attributes:
RO
READ ONLY
. If a register is read only, writes to this register have no effect.
R/W
READ/WRITE
. A register with this attribute can be read and written.
R/WC
READ/WRITE CLEAR
. A register bit with this attribute can be read and written. However, a write of
1 clears (sets to 0) the corresponding bit and a write of 0 has no effect.
Some of the MTXC registers described in this section contain reserved bits. Software must deal correctly with
fields that are reserved. On reads, software must use appropriate masks to extract the defined bits and not
rely on reserved bits being any particular value. On writes, software must ensure that the values of reserved
bit positions are preserved. That is, the values of reserved bit positions must first be read, merged with the
new values for other bit positions and then written back.
In addition to reserved bits within a register, the MTXC contains address locations in the PCI configuration
space that are marked “Reserved” (Table 3). The MTXC responds to accesses to these address locations by
completing the Host cycle and returning a value of zero. The registers marked as “Undefined” will return a
non-zero value and are defined as read only. Software should not write to reserved or undefined MTXC
configuration locations in the device-specific region (above address 3Fh).
Upon RESET, the MTXC sets its internal configuration registers to predetermined
default
states. The default
state represents the minimum functionality feature set required to successfully bring up the system. Hence, it
does not represent the optimal system configuration. It is the responsibility of the system initialization
software (usually BIOS) to properly determine the DRAM configurations, cache configuration, operating
parameters and optional system features that are applicable, and to program the MTXC registers accordingly.
3.1.
I/O Mapped Registers
The MTXC contains three registers that reside in the CPU I/O address space—the Configuration Address
(CONFADD) Register, the Configuration Data (CONFDATA) Register, and the PM2 Register Block. The
Configuration Address Register enables/disables the configuration space and determines what portion of
configuration space is visible through the Configuration Data window.
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相關(guān)代理商/技術(shù)參數(shù) |
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| FW82439TXSL28T | 功能描述:IC 82439TX SYS CTRL MTXC 324BGA RoHS:否 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
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