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| 型號(hào)： | FW82439TX |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項(xiàng)-數(shù)據(jù)表參考 |
| 文件頁數(shù)： | 13/102頁 |
| 文件大小： | 759K |
| 代理商： | FW82439TX |
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Extended Temperature 82439TX (MTXC) Datasheet
13
PRELIMINARY
2.1.3.
SECONDARY CACHE INTERFACE
Name
Type
Description
CADV#
O
3.3V
Cache Advance.
Assertion causes the PBSRAM in the secondary cache to
advance to the next QWord in the cache line.
CADS#
O
3.3V
Cache Address Strobe.
Assertion causes the PBSRAM in the secondary
cache to load the PBSRAM address register from the PBSRAM address pins.
CCS#
O
3.3V
Cache Chip Select (CCS#).
The second level cache will power up, if
necessary, and perform an access if this signal is asserted when CADS# is
asserted. The second level cache will power down if this signal is negated
when CADS# is asserted. When CCS# is negated the second level cache will
ignore ADS#. If CCS# is asserted when ADS# is asserted, the second level
cache will power up, if necessary, and perform an access.
COE#
O
3.3V
Cache Output Enable.
The secondary cache data RAMs drive the CPUs
data bus when COE# is asserted.
GWE#
O
3.3V
Global Write Enable.
GWE# assertion causes all the byte lanes to be written
into the secondary cache data RAMs, if they are powered up.
BWE#
O
3.3V
Byte Write Enable.
Asserted low with GWE#=HIGH to enable using host’s
BE[7:0]# to be used to control byte lanes to pipeline burst SRAM cache.
TIO[7:0]
I/O
3.3V/5V
Tag Address.
These are inputs during CPU accesses and outputs during
second level cache line fills and second level cache line invalidates due to
inquire cycles. These signals have internal pull-down resistors.
TWE#
O
3.3V
Tag Write Enable.
When asserted, new state and tag addresses are written
into the external tag.
KRQAK/
CS4_64#
I/O
3.3V
KRQAK/Chip Select 4 (for 64-Mb Technology).
This pin is a dual-function
signal. KRQAK is used in a DRAM Cache L2 implementation and is a
bi-directional refresh request/acknowledge. The CS4_64# function is used
to generate the fifth chip select line in a SDRAM L2 Cache implementation
that supports five rows of 64-Mbit SDRAM.
During a hard reset, this signal is sampled to determine if DRAM cache is in
the system (see MTXC Strapping options). This signal has a weak internal
pull-down.
If SDRAMC[bit 1]=1 and DRAM cache is not present in the system (indicated
by CEC[bit 5]=0, offset 53h), the CS4_64# function is selected. If DRAM
cache is in the system or SDRAMC[bit 1] (offset 54h)=0, then KRQAK is used
to drive the KRQAK function.
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| FW82439TXSL28T | 功能描述:IC 82439TX SYS CTRL MTXC 324BGA RoHS:否 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
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