參數(shù)資料
型號： FW82439TX
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項-數(shù)據(jù)表參考
文件頁數(shù)： 66/102頁
文件大?。?/td> 759K
代理商： FW82439TX
Extended Temperature 82439TX (MTXC) Datasheet
66
PRELIMINARY
As with the Compatible SMRAM solution, MTXC does not claim any bus master access to the Extended
SMRAM memory ranges defined above. The CPU can access these memory ranges by one of the following
mechanisms:
The processor generating an access to one of the defined memory ranges while in the SMM (SMIACT# is
active). A processor access to any of the defined ranges while not in SMM (SMIACT# is inactive) and
with the D_OPN bit reset will be forwarded to PCI bus and a status bit is set in the SMRAMC register.
The processor generating an access to one of the defined memory ranges while the D_OPN bit is set.
Any modified write access of the processor is allowed to write into the SMRAM space, regardless of the
state of the D_OPN, D_CLS, or SMIACT# signals.
The cacheability of SMRAM space is dependent on how much physical DRAM is available in the system. If
the system has less than 32 Mbytes of DRAM, the SMRAM is cached in both the L1 and L2. If the system
has more than 32 Mbytes of DRAM, the SMRAM is cached in only the L1.
4.5.3.
SMRAM PROGRAMMING CONSIDERATIONS
When using the Extended SMRAM configuration, the SMI handler software must be extremely careful when
accessing DRAM memory in the 100A0000h to 100FFFFFh memory range. First, if this area of memory is
accessed while the CPU is not in SMM mode and the D_OPN bit is not set, the MTXC will forward the cycle
to PCI bus which may cause a fatal system error and system shutdown. Second, only areas within the
100A0000h to 100FFFFFh region that have been selected as SMRAM space should be accessed; otherwise,
the L1 and L2 caches will become incoherent, which will cause a future system error. Any memory in normal
DRAM space that is not used in OS or application space can be used as SMRAM memory.
4.6.
Low Power States
MTXC supports five types of low power states: Chip Standby, Power On Suspend (POS), Suspend to RAM
(STR), Suspend to Disk (STD), and dynamic stop clock. The Table 20
summarizes the various MTXC’s Low
power states.
Table 20. 430TX Low Power State Summary
PM Mode
Description
Exit Latency Target
Chip Standby
When MTXC’s CPU and PCI busses are both idle, MTXC
enters this state.
No delay
Dynamic Stop
Clock
MTXC provides provisions that enable transitioning the CPU
in and out of the stop clock state in an active system. This
includes the ability to disable the system arbiter and transition
the memory controller in and out of the suspend refresh state.
<10 ms
Powered On
Suspend (POS)
System PLLs are powered down, only running clock is the
RTC clock and the SUSCLK. MTXC maintains DRAM refresh
using SUSCLK.
<10 ms
Suspend to RAM
(STR)
CPU complex (CPU and L2) and PCI interface are powered
off. Only the RTC clock and SUSCLK are running. MTXC
maintains DRAM refresh using SUSCLK.
~1 sec
Suspend to
Disk(STD)
CPU complex (CPU and L2), DRAM and PCI interface are
powered off.
~30 sec
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