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參數(shù)資料
| 型號(hào)： | FW82439TX |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項(xiàng)-數(shù)據(jù)表參考 |
| 文件頁數(shù)： | 32/102頁 |
| 文件大小： | 759K |
| 代理商： | FW82439TX |
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Extended Temperature 82439TX (MTXC) Datasheet
32
PRELIMINARY
3.1.17.
SDRAMC
SDRAM CONTROL REGISTER
Address Offset:
Default Value:
Access:
54–55h
0000h
Read/Write
Bit
Description
15:9
Reserved.
8:6
Special SDRAM Mode Select (SSMS).
These bits select 1 of 4 special SDRAM modes for
testing and initialization. Note that the NOP command must be programmed first before any other
command can be issued. After the DRAM detection process has completed, bits[7:5] must remain
at “000” during normal DRAM operation.
Bits[8:6]
Mode
000
Normal SDRAM mode (default).
001
NOP Command Enable (NOPCE).
This mode forces all CPU cycles to DRAM to
generate a SDRAM NOP command on the memory interface.
010
All Banks Precharge Command Enable (ABPCE).
This setting enables a mode
where all CPU cycles to DRAM are converted to an all banks precharge command on
the memory interface. Used for BIOS Detection algorithm.
011
Mode Register Command Enable (MRCE).
This setting enables a mode where all
CPU cycles to DRAM are converted into MRS commands to the memory interface.
The command is driven on the MA[11:0] lines. MA[2:0] needs to be always driven to
010 for burst of 4 mode. MA3 needs to be always driven to 1 for interleave wrap type
mode. MA4 needs to be driven to the value in the CAS# Latency bit. MA[6:5] needs
to be always driven to 01. MA[11:7] needs to be always driven to 00000.
The BIOS will select an appropriate host address for each Row of memory such that
the right commands are generated on the Memory Address MA[11:0] lines. The BIOS
needs to be cognizant of the mapping of the Host addresses to Memory addresses.
e.g. A Host address of 1D0h will set up the Mode registers in Row 0 of SDRAM with
Burst length of 4, Wrap type of interleaved, and CAS latency of 3.
100
CBR Cycle Enable (CBRC).
This setting enables a mode where all CPU cycles to
DRAM are converted to SDRAM CBR refresh cycles on the memory interface.
101
Reserved
11X
Reserved
5
RAS# to CAS# Override (RCO)
.
When set to 1, and the CL bit (CAS Latency) is 0 (CAS
Latency=3), then a RAS# to CAS# delay of 2 HCLKs is provided for SDRAM
.
When set to 0, a
RAS# to CAS# delay for SDRAM is determined by the CL bit
.
4
CAS# Latency (CL).
When set to 1, a CAS# latency of 2 is used for all SDRAM cycles. When
reset to 0, CAS# latency of 3 is used for all SDRAM cycles.
3
RAS# Timing (RT).
This bit controls RAS# precharge, RAS# active to precharge time and
Refresh to RAS# active delay (in HCLKs):
Bit 3
RAS#
RAS# act.
Refresh to
Precharge
to Precharge
RAS# act.
0
3
5
1
3
4
8
7
2
Reserved.
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