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參數資料
| 型號： | FW82439TX |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項-數據表參考 |
| 文件頁數： | 16/102頁 |
| 文件大?。?/td> | 759K |
| 代理商： | FW82439TX |
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Extended Temperature 82439TX (MTXC) Datasheet
16
PRELIMINARY
2.2.
MTXC Strapping Options
Name
Type
Description
SCS
A[31:30]
Secondary Cache Size.
Described in the Cache Control Register bits 7:6.
L2RAMT
A[29:28]
Initial L2 RAM Type.
Described in the Cache Control Register bits 5:4.
DRAM
Cache
KRQAK
DRAM Cache L2 Present Upon Reset Negation.
This bit is sampled to detect
DRAM L2 cache. If sampled high, a DRAM Cache is present. A weak pulldown is
provided internally. A DRAM cache module should implement a pull-up on this pin
that overrides the weak pulldown. BIOS does not have to be aware of this, this
information is used by the MTXC to maintain optimal Pburst timings.
25VD
A26
2.5V Voltage Detection.
This bit is used to determine the voltage level (3.3V or
2.5V) of the host clock connected to the host clock pin and the voltage on the
V
CC
(CPU) pins. An external pull-down or pull-up resistor is required on this pin
(pulled down for 2.5V and pulled up for 3.3V).
HFD
A27
Frequency Detection.
BIOS can use this bit to determine if the system is 60 MHz
(external pull-up) or 66 MHz (no strapping is present) as described in the DRTH
Register, bit 7. DRTH[bit 7] register is initialized with the inverted value of pin A27
upon reset negation. The A27 input buffer includes a weak pulldown resistor which
will force DRTH[bit 7] to default to 1 if no strapping is present.
2.3.
Power Planes
The MTXC has three primary internal power planes. These power planes permit parts of the MTXC to power
down to conserve battery life. Table 1 shows the internal planes and their uses.
Table 1. MTXC Internal Power Planes
Power
Plane
Description
Signals Powered
V
CC
Pins
GND
Pins
SUSPEND
Contains the logic needed to resume from the
Suspend-to-RAM state. This power supply
should be capable of providing a “trickle” current.
The input signals attached to the SUSPEND
power plane Do Not Support 5V Input Levels.
These signals must not exceed V
CC
(SUS).
MWE#, MWEB#,
CKE, RAS[5:0]#
1
,
CAS[7:0]#, SUSCLK,
SUSSTAT1#
V
CC
(SUS)
V
SS
CPU
CPU Interface signals have a separate supply so
that the CPU interface can be 3.3V for existing
CPUs and can be 2.5V on future CPUs.
A[31:3], BE[7:0]#,
ADS#, BRDY#, NA#,
AHOLD, EADS#,
BOFF#, HITM#,
M/IO#, D/C#, W/R#,
HLOCK#, CACHE#,
KEN#/INV, SMIACT#,
HD[63:0], HCLKIN
V
CC
(CPU)
V
SS
V
CC
5REF
The V
CC
5REF signal provides protection for the
5V tolerant 3.3V signals.
PCI Bus Input and
I/O, MD[63:0],
TIO[7:0], PCLKIN,
TEST#
V
CC
5REF
V
SS
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