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參數(shù)資料
| 型號： | FW82439TX |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項-數(shù)據(jù)表參考 |
| 文件頁數(shù)： | 11/102頁 |
| 文件大?。?/td> | 759K |
| 代理商： | FW82439TX |
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Extended Temperature 82439TX (MTXC) Datasheet
11
PRELIMINARY
2.1.2.
DRAM INTERFACE
Name
Type
Description
RAS[3:0]#
or
CS[3:0]#,
RAS4#/CS4#/
BA1,
RAS5#/CS5#/
MA13
O
3.3 V
Row Address Strobe—RASx# (EDO/FPM).
These pins select the DRAM row.
Chip Select—CSx# (SDRAM).
These pins activate the SDRAMs. SDRAM
accepts any command when its CS# pin is active low.
Note: For 64Mbit SDRAM support, BA1/MA12 and MA13 are muxed with the
RAS4# and RAS5# signals, respectively. When SDRAMC[bit 1]=1, BA1 and
MA13 are driven out on these lines.
CAS[7:0]# or
DQM[7:0]
O
3.3 V
Column Address Strobe (EDO/FPM).
These pins select the DRAM column.
Input/Output Data Mask SDRAM).
These pins act as synchronized output
enables during a read cycle and a byte mask during a write cycle. The read
cycles require Tdqz clock latency before the functions are actually performed. In
case of a write cycle, word mask functions are performed in the same cycle (0
cycle latency).
MA[11:0]
O
3.3 V
Memory Address (EDO/FPM/SDRAM).
This is the row and column address for
DRAM. These buffers now include programmable size selection, as controlled by
the DRAMEC[MAD] bit. For 64-Mbit SDRAM support BA1/MA12 and MA13 are
muxed with the RAS4# and RAS5# signals, respectively.
MWEB#
O
3.3 V
Memory Write Enable (second copy) (EDO/FPM/SDRAM).
MWE# should be
used as the write enable for the memory data bus. This signal has programmable
buffer size selection.
MWE#
O
3.3 V
Memory Write Enable (EDO/FPM/SDRAM).
MWE# should be used as the write
enable for the memory data bus. This signal has programmable buffer size
selection.
SRAS[A,B]#
O
3.3 V
SDRAM Row Address Strobe (SDRAM).
When asserted, this signal latches
Row Address on the positive edge of the clock. This signal also allows Row
access and precharge. Two copies are provided for loading purpose. These
signals have programmable buffer size selection.
SCAS[A,B]#
O
3.3 V
SDRAM Column Address Strobe (SDRAM).
When asserted, this signal latches
Column Address on the positive edge of the clock. This signal also allows
Column access. Two copies provided for loading purpose. These signals have
programmable buffer size selection.
CKE/MAA0
O
3.3 V
SDRAM Clock Enable (SDRAM).
SDRAM
clock enable pin. When this signal is
negated, SDRAM enters power down mode. This signal is also muxed to provide
a second copy of memory address MA0 (MAA0). The MA function is selected via
DRT[bit2] (offset 67h).
MTXC negates CKE (and CKEB) when SUSSTAT1# is asserted. Note that
MTXC asserts CKE (and CKEB) for all rows (i.e., CKE and CKEB cannot be
selectively asserted for certain rows and negated for other rows).
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| FW82439TXSL28T | 功能描述:IC 82439TX SYS CTRL MTXC 324BGA RoHS:否 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
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