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參數(shù)資料
| 型號： | FW82439TX |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項-數(shù)據(jù)表參考 |
| 文件頁數(shù)： | 69/102頁 |
| 文件大小： | 759K |
| 代理商： | FW82439TX |
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Extended Temperature 82439TX (MTXC) Datasheet
69
PRELIMINARY
synchronized to the PCI clock. To not reset the suspend well within the MTXC, the PIIX4 will drive the
SUS_STAT# signal just after the SUSCLK signal has gone high. To reset the resume well within the MTXC,
the PIIX4 will drive the SUS_STAT# signal while the SUSCLK is disabled (low). Because of this functionality,
SUSCLK should not be inverted for any reason in applications.
4.7.
PCI Interface
The MTXC integrates a high performance interface to the PCI local bus taking full advantage of the high
bandwidth and low latency of PCI. The MTXC is fully PCI 2.1 compliant. Table 22 lists the PCI bus
commands supported. Five PCI masters are supported by the integrated arbiter including the PIIX4 and four
general PCI masters. The MTXC acts as a PCI master for CPU accesses to PCI. The PCI bus is clocked at
one half the frequency of the CPU clock. This divided synchronous interface minimizes latency for CPU-to-
PCI cycles and PCI-to-main memory cycles.
The MTXC integrates posted write buffers for CPU memory writes to PCI. Back-to-back sequential memory
writes to PCI are converted to burst writes on PCI. This feature allows the CPU to continue posting DWord
writes at the maximum bandwidth for the Pentium processor for the highest possible transfer rates to the
graphics frame buffer.
Read prefetch and write posting buffers in the MTXC enable PCI masters to access main memory at up to
120 MB/sec. The MTXC incorporates a snoop ahead feature that allows PCI masters to continue bursting on
both reads and writes even as the bursts cross cache line boundaries.
The MTXC forwards each of the CPU shutdown, Halt, and Stop Grant cycles to the PCI bus as special
cycles. These cycles are terminated on PCI as master abort and a BRDY# is returned to the CPU. The Stop
Grant cycle is propagated with 0002h in the message field and 0012h in the message dependent data field.
Table 22. PCI Commands
C/BE#
Command
Target Support
Initiator Support
0000
Interrupt Acknowledge
NO
YES
0001
Special cycle
NO
YES
0010
I/O read
YES
YES
0011
I/O write
YES
YES
0100
reserved
NO
NO
0101
reserved
NO
NO
0110
Memory read
YES
YES
0111
Memory write
YES
YES
1000
reserved
NO
NO
1001
reserved
NO
NO
1010
Configuration Read
NO
YES
1011
Configuration Write
NO
YES
1100
Memory Read Multiple
As Memory Read
NO
1101
Dual Address Cycle
NO
NO
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參數(shù)描述 |
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