參數(shù)資料
型號： FW82439TX
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項-數(shù)據(jù)表參考
文件頁數(shù)： 44/102頁
文件大小： 759K
代理商： FW82439TX
Extended Temperature 82439TX (MTXC) Datasheet
44
PRELIMINARY
3.1.26.
ESMRAMC
EXTENDED SYSTEM MANAGEMENT RAM CONTROL REGISTER
Address Offset:
Default Value:
Access:
71h
00h
Read/Write
The Extended SMRAM register controls the configuration of Extended SMRAM space. MTXC supports two
types of SMRAM memory: Compatible and Extended. The Compatible SMRAM (C_SMRAM) memory
provides an uncacheable SMRAM memory space below 1 Mbytes in the A and B segments. The Extended
SMRAM (E_SMRAM) memory provides a writeback cacheable SMRAM memory space that is above 1
Mbytes. This register provides the following types of control over SMRAM space:
Where the memory space is located (above 1 Mbytes, below 1 Mbytes)
Enabling of SMRAM memory (TSEG, 128 Kbytes, 256 Kbytes, 512 Kbytes or 1 Mbytes of additional
SMRAM memory) for Extended SMRAM space only.
Cacheability control (for the Extended SMRAM space only)
Protection of SMRAM space for non-SMM accesses
Bit
Description
7
High SMRAM Enable (H_SMRAME)
.
1=Enable. 0=Disable. This bit enables the high SMRAM
memory space to appear in the appropriate physical address locations between 100A0000h and
100F0000h.
6
Extended SMRAM Error (E_SMERR)
.
This bit is set when CPU accesses the defined memory
ranges in Extended SMRAM (High Memory and T-segment) while not in SMM space and with the
D-OPEN bit=0. It is software’s responsibility to clear this bit. The software must write a 1 to this
bit
to clear it.
5
SMRAM Cache Strategy (SM_CACHE)
.
Hardwired to 0. This bit determines how Extended
SMRAM space is cached (writethru or writeback). Since the MTXC supports only writeback for
extended SMRAM space, this bit is hardwired to 0.
4
SMRAM_L1_EN (SM_L1)
.
This bit should be set to 1 if Extended SMRAM is being used and the
system wishes to L1 writeback cache this memory space. Default value for this bit is 0.
3
SMRAM_L2_EN (SM_L2).
This bit should be set to 1 if Extended SMRAM is being used, and
there is less than 32 Mbytes of DRAM in the system. Setting of this bit when SM_L1 bit=1 allows
the Extended SMRAM to be writeback cached in the L2. Default value for this bit is 0.
2:1
TSEG_SZ[1-0] (T_SZ)
.
Selects the size of the TSEG memory block, if enabled. This memory is
taken from the top of DRAM space, which is no longer claimed by the memory controller (all
accesses to this space are sent to the PCI bus if TSEG_EN is set). This memory appears at the
physical memory space of 256 Mbytes plus the top of memory (TOM) minus the size of TSEG.
This field decodes as follows:
Bits[1,0]
00
01
10
11
Description
(TOM-128 KB) to TOM
(TOM-256 KB) to TOM
(TOM-512 KB) to TOM
(TOM-1 MB) to TOM
0
TSEG_EN (T_EN)
.
When G_SMRAME=1 and T_EN=1, the TSEG is enabled to appear in the
appropriate physical address space.
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