參數(shù)資料
型號(hào)： FW82439TX
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項(xiàng)-數(shù)據(jù)表參考
文件頁(yè)數(shù)： 52/102頁(yè)
文件大小： 759K
代理商： FW82439TX
Extended Temperature 82439TX (MTXC) Datasheet
52
PRELIMINARY
4.2.3.
DRAM CACHE SECOND LEVEL CACHE MODE
DRAM Cache L2 cache implementation is similar to Pipelined Burst SRAM, except for the addition of the
KRQAK bi-direct refresh handshake signal between the MTXC and L2 SRAM. A DRAM Cache type L2 is
assumed present when the KRQAK pin is sampled high during the negation of the reset signal. An internal
weak pull-down is used on the MTXC KRQAK pin to default to a non DRAM Cache L2 mode, if this pin is left
unconnected. An external pull-up (10 k
) must be used on KRQAK when DRAM Cache SRAM is used. Note
that there is no configuration bit associated with the L2 Pseudo SRAM mode.
The SRAM can operate in either master or slave mode via the M/S# strapping bit. In master mode, the SRAM
drives the KRQAK pin to request a refresh. A slave device never drives KRQAK, but only monitors it to
determine when a refresh period begins. Only one SRAM device within the L2 cache is master enabled. The
other SRAM devices must be slaves.
During reset, the master SRAM and MTXC tri-state their KRQAK outputs. After the SRAM RESET pin is
negated, KRQAK remains tri-stated for one whole refresh interval and is then driven high by the master
SRAM. The SRAM signals a refresh request by driving KRQAK low for 1 clock, high the next clock, and then
tri-states on the following clock and waits, sampling the KRQAK pin. The MTXC after sampling the SRAM’s
request on KRQAK and after the SRAM has tri-stated its KRQAK output, waits for a host bus dead clock and
grants an L2 refresh by driving its KRQAK pin in an identical fashion to the SRAM’s request signaling. When
all SRAM’s see the refresh grant from the MTXC, they begin their internal refresh cycle for a period of 20
clocks.
4.3.
DRAM Interface
The MTXC integrates a DRAM controller that supports a 64-bit memory array from 4 Mbytes to 256 Mbytes of
main memory. The MTXC supports Standard Page Mode (FPM), Extended Data Out (EDO) and
Synchronous DRAM (SDRAM) memories using 32-bit wide SIMM modules, 64-bit wide unbuffered DIMM
modules and 64-bit wide unbuffered SO-DIMM modules. DRAM parity is not supported, and for loading
reasons, parity modules should not be used. All three memory types can be mixed and matched. The MTXC
generates all DRAM control signals and multiplexed addresses for the DRAM array. The address and data
flows through the MTXC for all DRAM accesses. The DRAM controller interface is fully configurable through a
set of control registers. Complete descriptions of these registers are given in the MTXC configuration register
description. A brief overview of these registers is provided in this section.
The MTXC supports page mode DRAMs and EDO (Extended Data Out) DRAMs; otherwise known as Hyper
Page mode. The twelve multiplexed address lines, MA[11:0], allow the MTXC to support 4-Mbit, 16-Mbit, and
64-Mbit memory, both symmetrical and asymmetrical addressing. The MTXC has six RAS# lines enabling the
support of up to six rows of DRAM. Eight CAS# lines allow byte control over the array during write operations.
The MTXC targets 60 ns (also supports 50 ns and 70 ns) DRAMs, and supports both single- and double-
sided Dram modules. The MTXC provides CBR refresh and extended CBR refresh in the normal mode and
self refresh or CBR (for EDOs only) during suspend mode.
The MTXC also supports SDRAMs. The fourteen multiplexed address lines, MA[13:0], allow the MTXC to
support 16-Mbit and 64-Mbit SDRAM devices. The MTXC has six CS# lines (i.e. muxed onto RAS#[5:0]).
Although six CS# signals are provided, due to loading concerns, 5 rows of SDRAM maximum is
recommended. Eight DQM lines (i.e., muxed with CAS#[7:0]) allow byte control over the array during the write
operation. Two copies of SRAS# and SCAS# signals are provided for encoded SDRAM commands. The
MTXC targets 60- and 66-MHz SDRAMs and supports both single- and double-sided SDRAM modules.
The DRAM interface of the MTXC is configured by the DRAM Control Mode Register (DRAMC), DRAM
Extended Control Register (DRAMEC), DRAM Timing Register (DRAMT), SDRAM Control Register
(SDRAMC), six DRAM Row Boundary (DRB) Registers, and the DRAM Row Type (DRT) Registers. The DRB
registers define the size of each row in the memory array.
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FW82439TX S L28T 制造商:Intel 功能描述:System Controller 324-Pin BGA
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