參數(shù)資料
型號(hào)： FW82439TX
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項(xiàng)-數(shù)據(jù)表參考
文件頁數(shù)： 102/102頁
文件大小： 759K
代理商： FW82439TX
Extended Temperature 82439TX (MTXC) Datasheet
102
PRELIMINARY
11.0. ERRATA
11.1.
SDRAM Speculative Read Enable (SSRE)
P
ROBLEM
:
Due to a timing marginality during SDRAM read-page-hit cycles, the SSRE mode does not
function properly and must be disabled. This mode provided a five clock read lead off during CPU read-page-
hit cycles to main memory. This mode impacts SDRAM only.
I
MPLICATION
:
If SSRE mode is enabled, the system may not function properly. Intel has tested this mode
and found the performance impact of disabling the SSRE mode is less than 0.20% for Winstone ’96 and
Winstone ’97 benchmarks on the 430TX reference platform with 200MHz Pentium processor with MMX
technology, 16MB SDRAM, 512K PBSRAM L2, and hard drive in PIO Mode 4,
W
ORKAROUND
:
This errata is avoided by disabling the SSRE mode by clearing bit 7 in register offset 56h to
“0”. This bit has been changed to a reserved bit and must always remain in its default state (0).
S
TATUS
:
There are no plans to fix this erratum.
11.2.
Fast Back-to-Back, PCI Peer-to-Peer Cycles
P
ROBLEM
:
If a fast back-to-back cycle occurs on the PCI bus between the same master peer device and the
same slave peer device (i.e. MTXC and PIIX4 are not the intended targets), and at the same time a CPU
cycle to PCI occurs, the MTXC may miss the second peer-to-peer cycle in the back-to-back sequence. The
specific conditions that need to be met for this to occur, are as follows:
1. The PCI peer-to-peer, back-to-back transfer must happen at the same time the CPU is
generating a host cycle to PCI. Specifically, between the rising edge of the first FRAME#
(associated with the first cycle of the back-to-back transfer) to the rising edge of the second
FRAME# (associated with the second cycle in the back-to-back transfer).
2. The PCI back-to-back transfer must be peer-to-peer and the transfer must not be targeting the
PIIX4 or the MTXC.
3. The PCI master must be capable of running “fast” back-to-back cycles.
4. The second cycle of the back-to-back transfer must be targeting the same PCI slave device.
5. The PCI slave device must be doing a “fast” decode.
6. The first cycle in the back-to-back transfer must be a single transfer.
7. The first cycle in the back-to-back transfer must be a PCI write cycle (memory or I/O).
I
MPLICATION
:
Intel observed this issue in a system simulation environment.
W
ORKAROUND
:
If deemed necessary by the OEM, this issue can be avoided by clearing bit 3 in register
offset 50h to “0”. When set to “0”, this bit prevents CPU bus access during PCI peer-to-peer transfers.
S
TATUS
:
There are no plans to fix this erratum.
相關(guān)PDF資料
PDF描述
FW82815 Controller Miscellaneous - Datasheet Reference
FWA-25A10F Fuse
FWA-30A10F Fuse
FWA-35A21F Fuse
FWA-40A21F Fuse
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
FW82439TX S L28T 制造商:Intel 功能描述:System Controller 324-Pin BGA
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