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參數(shù)資料
| 型號： | FW82439TX |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項-數(shù)據(jù)表參考 |
| 文件頁數(shù)： | 6/102頁 |
| 文件大?。?/td> | 759K |
| 代理商： | FW82439TX |
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Extended Temperature 82439TX (MTXC) Datasheet
6
PRELIMINARY
1.0.
ARCHITECTURE OVERVIEW
The MTXC host bridge provides a completely integrated solution for the system controller and datapath
components in a Pentium processor system. The MTXC Supports all Pentium family processors since P54C,
it has 64-bit Host and DRAM Bus Interface, 32-bit PCI Bus Interface, Second level Cache Interface, and it
integrates the PCI arbiter.
The MTXC interfaces with the Pentium processor host bus, a dedicated memory data bus, and the PCI bus
(see Figure 1).
The MTXC bus interfaces are designed to interface with 2.5V, 3.3V and 5V busses. The MTXC implements
2.5V and 3.3V drivers and 5V tolerant receivers. The MTXC connects directly to the Pentium processor 3.3V
or 2.5V host bus, directly to 5V or 3.3V DRAMs, and directly to the 5V or 3.3V PCI bus. The 430TX also
interfaces directly to the 3.3V or 5.0V TAGRAM and 3.3V Cache.
The MTXC works with the PCI IDE/ISA Accelerator 4 (PIIX4). The PIIX4 provides the PCI-to-ISA/EIO bridge
functions along with other features such as a fast IDE interface (PIO mode 4 and Ultra DMA/33), Plug-n-Play
port, APIC interface, PCI 2.1 Compliance, SMBUS interface, and Universal Serial Bus Host Controller
functions.
DRAM Interface
The DRAM interface is a 64-bit data path that supports Standard (or Fast) Page Mode (FPM), Extended Data
Out (EDO) and Synchronous DRAM (SDRAM) memory. The DRAM controller inside the MTXC is capable of
generating 3-1-1-1 for posted writes for any type of DRAM that is used. While read performance is 6-1-1-1 for
SDRAM, 5-2-2-2 for EDO, and 6-3-3-3 for FPM.
The DRAM interface supports 4 Mbytes to 256 Mbytes with six RAS lines. The MTXC supports 4-Mbit, 16-
Mbit, and 64-Mbit DRAM and SDRAM technology, both symmetrical and asymmetrical. Parity is not
supported, and for loading reasons, x32 and x64 SIMMs/DIMMs/SO-DIMMs should be used.
Second Level Cache
The second level cache is direct mapped and supports both 256-Kbyte and 512-Kbyte SRAM configuration
using Pipeline Burst SRAM or DRAM Cache SRAM. The Cache performance is 3-1-1-1 for line read/write and
3-1-1-1-1-1-1-1 for back to back reads that are pipelined. Cacheless configuration is also supported.
PCI Interface
The PCI interface is 2.1 compliant and supports up to four PCI bus masters in addition to the PIIX4 bus
master requests.
Datapath and Buffers
The MTXC contains three sets of data buffers for optimizing data flow. A five QWord deep DRAM write buffer
is provided for CPU-to-DRAM writes, second level cache write backs, and PCI-to-DRAM transfers. This buffer
is used to achieve 3-1-1-1 posted writes to DRAM and also provides DWord merging and burst merging for
CPU-to-DRAM write cycles. In addition, an extra line of buffering is provided that is combined with the DRAM
Write Buffer to supply an 18 DWord deep buffer for PCI to main memory writes. A five DWord buffer is
provided for CPU-to-PCI writes to help maximize the bandwidth for graphic writes to the PCI bus. Also, five
QWords of prefetch buffering has been added to the PCI-to-DRAM read path that allows up to two lines of
data to be prefetched at an x-2-2-2 rate. The MTXC interfaces directly to the Host and DRAM data bus.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| FW82439TX S L28T | 制造商:Intel 功能描述:System Controller 324-Pin BGA |
| FW82439TX S L3BT | 制造商:Intel 功能描述:System Controller |
| FW82439TX S L28T | 制造商:Intel 功能描述: |
| FW82439TX S L3BT | 制造商:Intel 功能描述:System Controller |
| FW82439TXSL28T | 功能描述:IC 82439TX SYS CTRL MTXC 324BGA RoHS:否 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標準包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應商設備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
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