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參數(shù)資料
| 型號： | FW82439TX |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項-數(shù)據(jù)表參考 |
| 文件頁數(shù)： | 42/102頁 |
| 文件大小： | 759K |
| 代理商： | FW82439TX |
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Extended Temperature 82439TX (MTXC) Datasheet
42
PRELIMINARY
3.1.23.
DRTH
DRAM ROW TYPE REGISTER HIGH
Address Offset:
Default Value:
Access:
67h
S0000000
Read/Write
This 8-bit register identifies the type of DRAM (EDO, SPM (standard page mode)), or SDRAM (synchronous
DRAM) used in rows 4 and 5 and should be programmed by BIOS for optimum performance if EDO DRAMs
or SDRAMs are used. The MTXC uses these bits to determine the correct cycle timing to use before a DRAM
cycle is run. Bit 7 of this register is used for Host Frequency Detection (HFD). Bit 2 of this register is used to
determine the muxing results of CKE/MAA0 and CKEB/MAA1.
NOTE
This register should not be written while DRAM refresh is enabled.
Bit
Description
7
Host Frequency Detection (HFD)
.
1=66 MHz. 0=60 MHz. This bit is initialized to the inverted
level on the A27 signal at the rising edge of the RST#. Since A27 pin contains an internal weak
pulldown, unless an external resistor exits, the field is initialized to 1, indicating 66 MHz.
Subsequent writes to this field will override the reset strap value. BIOS can use the value to
determine if the system is
60 MHz (external pull-up) or 66 MHz (no strapping).
5:4,
1:0
DRAM Row Type (DRT).
The DRT bits select the DRAM type installed in each physical DRAM
Row. Each one-of-four bit pairs in this register corresponds to the DRAM row identified by the
corresponding DRB register.
DRT Bits
5,1
4,0
DRAM Row
5
4
DRT
0,0
0,1
1,0
1,1
DRAM Type value definitions
SPM DRAM
EDO DRAM
SDRAM
Reserved
6,3
Reserved.
2
Memory Address Select Enable (MASELEN).
When this bit is set to 1, CKE and CKEB are
used to propagate the second copy of the MA0 and MA1 lines. CKE is muxed with MAA0 and
CKEB is muxed with MAA1. When this bit is set to 0, the CKE and CKEB functionality is
propagated across these lines. This bit defaults to 0 and BIOS must set it to 1 to take advantage
of the second copy of the MA0 and MA1 lines.
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相關代理商/技術參數(shù) |
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