參數(shù)資料
型號(hào)： FW82439TX
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項(xiàng)-數(shù)據(jù)表參考
文件頁(yè)數(shù)： 37/102頁(yè)
文件大?。?/td> 759K
代理商： FW82439TX
Extended Temperature 82439TX (MTXC) Datasheet
37
PRELIMINARY
3.1.21.
PAM
PROGRAMMABLE ATTRIBUTE MAP REGISTERS (PAM[6:0])
Address Offset:
Default Value:
Attribute:
Size:
59h (PAM0) (5Fh (PAM6)
00h
Read/Write
8 bits (each register)
The MTXC allows programmable memory and cacheability attributes on 14 memory segments of various
sizes in the 640-Kbytes to 1-Mbyte address range. Seven Programmable Attribute Map (PAM) Registers are
used to support these features. Three bits are used to specify L1 cacheability and memory attributes for each
memory segment. These attributes are:
RE
Read Enable
. When RE=1, the CPU read accesses to the corresponding memory segment are
directed to main memory. Conversely, when RE=0, the CPU read accesses are directed to PCI.
WE
Write Enable
. When WE=1, the CPU write accesses to the corresponding memory segment are
directed to main memory. Conversely, when WE=0, the CPU write accesses are directed to PCI.
CE
Cache Enable
. When CE=1, the corresponding memory segment is L1 cacheable. CE must not be
set to 1 when RE is reset to 0 for any particular memory segment. When CE=1 and WE=0, the
corresponding memory segment is cached in the first level cache only on CPU code read cycles.
The RE and WE attributes permit a memory segment to be Read Only, Write Only, Read/Write, or disabled.
For example, if a memory segment has RE=1 and WE=0, the segment is Read Only. The characteristics for
memory segments with these read/write attributes are described in Table 5.
Table 5. Attribute Definition
Read/Write
Attribute
Definition
Read Only
Read cycles: CPU cycles are serviced by the DRAM in a normal manner.
Write cycles: CPU initiated write cycles are ignored by the DRAM interface as well as
the cache. Instead, the cycles are passed to PCI for termination.
Areas marked as Read Only are L1 cacheable for Code accesses only. These regions
are not cached in the second level cache.
Write Only
Read cycles: All read cycles are ignored by the DRAM interface as well as the second
level cache. CPU-initiated read cycles are passed onto PCI for termination. The write
only state can be used while copying the contents of a ROM, accessible on PCI, to
main memory for shadowing, as in the case of BIOS shadowing.
Write cycles: CPU write cycles are serviced by the DRAM and L2 cache in a normal
manner.
Read/Write
This is the normal operating mode of main memory. Both read and write cycles from the
CPU and PCI are serviced by the DRAM and L2 cache interface.
Disabled
All read and write cycles to this area are ignored by the DRAM and cache interface.
These cycles are forwarded to PCI for termination.
相關(guān)PDF資料
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參數(shù)描述
FW82439TX S L28T 制造商:Intel 功能描述:System Controller 324-Pin BGA
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