參數(shù)資料
型號: FW82439TX
英文描述: Controller Miscellaneous - Datasheet Reference
中文描述: 控制器雜項-數(shù)據(jù)表參考
文件頁數(shù): 4/102頁
文件大?。?/td> 759K
代理商: FW82439TX
Extended Temperature 82439TX (MTXC) Datasheet
4
PRELIMINARY
3.1.21. PAM
PROGRAMMABLE ATTRIBUTE MAP REGISTERS (PAM[6:0]) ....................................37
DOS Application Area (00000h–9FFFh).............................................................................................39
Video Buffer Area (A0000h–BFFFFh) ................................................................................................39
Expansion Area (C0000h–DFFFFh)...................................................................................................39
Extended System BIOS Area (E0000h–EFFFFh)...............................................................................39
System BIOS Area (F0000h–FFFFFh)...............................................................................................39
Extended Memory Area (100000h–FFFFFFFFh) ...............................................................................39
3.1.22. DRB
DRAM ROW BOUNDARY REGISTERS.........................................................................40
3.1.23. DRTH
DRAM ROW TYPE REGISTER HIGH..........................................................................42
3.1.24. DRTL—DRAM ROW TYPE REGISTER LOW............................................................................43
3.1.25. MTT
MULTI-TRANSACTION TIMER REGISTER (RESERVED TEST MODE REGISTER)....43
3.1.26. ESMRAMC
EXTENDED SYSTEM MANAGEMENT RAM CONTROL REGISTER..................44
3.1.27. SMRAMC
SYSTEM MANAGEMENT RAM CONTROL REGISTER ........................................45
3.1.28. MCTL
MISCELLANEOUS CONTROL REGISTER..................................................................47
4. 0. FUNCTIONAL DESCRIPTION............................................................................................................48
4.1.
Host Interface.................................................................................................................................48
4.2.
Secondary Cache Interface............................................................................................................48
4.2.1. CLOCK LATENCIES....................................................................................................................51
4.2.2. SNOOP CYCLES ........................................................................................................................51
4.2.3. DRAM CACHE SECOND LEVEL CACHE MODE........................................................................52
4.3.
DRAM Interface..............................................................................................................................52
4.3.1. DRAM ORGANIZATION..............................................................................................................53
4.3.2. CONFIGURATION REQUIREMENTS .........................................................................................55
4.3.3. DRAM ADDRESS TRANSLATION..............................................................................................59
4.3.4. DRAM PAGING...........................................................................................................................59
4.3.5. DRAM TYPES .............................................................................................................................59
4.3.5.1. FPM Mode ............................................................................................................................59
4.3.5.2. EDO Mode ............................................................................................................................59
4.3.5.3. SDRAM Mode.......................................................................................................................59
4.3.6. AUTO DETECTION.....................................................................................................................61
4.3.7. DRAM PERFORMANCE..............................................................................................................61
4.3.8. DRAM REFRESH........................................................................................................................64
4.4.
PCI CLK Control (CLKRUN#).........................................................................................................64
4.4.1. CLOCKING STATES...................................................................................................................64
4.4.2. OPERATION................................................................................................................................64
4.5.
SMRAM Memory Space.................................................................................................................64
4.5.1. COMPATIBLE SMRAM (C_SMRAM) ..........................................................................................64
4.5.2. EXTENDED SMRAM (E_SMRAM)..............................................................................................64
4.5.3. SMRAM PROGRAMMING CONSIDERATIONS..........................................................................66
4.6.
Low Power States ..........................................................................................................................66
4.6.1. CHIP STANDBY..........................................................................................................................67
4.6.2. SUSPEND/RESUME...................................................................................................................67
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