參數(shù)資料
型號： FW82439TX
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項-數(shù)據(jù)表參考
文件頁數(shù)： 67/102頁
文件大?。?/td> 759K
代理商： FW82439TX
Extended Temperature 82439TX (MTXC) Datasheet
67
PRELIMINARY
The 430TX system maintains a very low power CPU complex by utilizing the different power down features
available from the CPU, cache data RAMs and utilizing leading edge low power design techniques in the
430TX system components. The 430TX components work in unison to dynamically control the CPU
complexes power state without adversely affecting performance. The following gives a brief description of
how the 430TX system components achieve these low power states.
The MTXC and PIIX4 work in unison to maintain a very low power L2 subsystem without adversely affecting
peak performance.
NOTE
There are some system restrictions when DRAM Cache is implemented in a system that supports
STP_CLK, POS, and STR power management modes. Since KRQAK is not implemented in the
“Suspend Well,” the correct operation of KRQAK is not guaranteed when the system enters the above
mentioned power management modes. To avoid data corruption in the L2 cache, a system that
implements the STP_CLK, POS, and STR modes must abide by the following rules:
1.
Before entering these power management modes, the DRAM cache must be flushed so that all
modified lines end up in system memory.
2.
After exiting these power management modes, the DRAM Cache must be reinitialized.
4.6.1.
CHIP STANDBY
The MTXC also supports a chip standby mode. When the MTXC determines that both its CPU interface and
PCI interface are idle, it will dynamically place itself into a very low power state. While in chip standby state
the MTXC is able to respond to new CPU or PCI bus master accesses with no performance penalty. This
provides very optimized power/performance characteristics because the CPU interface are idle for large
periods of time. The MTXC enters Chip Standby mode when the following conditions are true:
Host Bus idle
PCI bus Idle
Normal Mode (i.e., not Test Mode)
Not in RESET state
Internal operations idle
Entering the Chip Standby state is not dependent on any timer expiration. When the above conditions are
met, the MTXC can enter the chip standby state as soon as it can.
4.6.2.
SUSPEND/RESUME
The MTXC supports POS, STR, STD and SOFF (Soft Off) suspend states. The MTXC supports the POS
mode by maintaining all of its power planes when in the suspend state. The MTXC supports the STR modes
by isolating its CPU and PCI interfaces, and only maintaining the DRAM refresh off the SUSCLK signal.
When exiting the STR modes, the MTXC’s core well is reset and its context is lost (the power management
context is not lost however). The MTXC supports the STD and SOFF modes by being totally powered off.
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