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參數(shù)資料
| 型號(hào)： | DS34S132GN+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 177/194頁 |
| 文件大小： | 0K |
| 描述： | IC TDM OVER PACKET 676-BGA |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 40 |
| 功能： | TDM-over-Packet（TDMoP） |
| 接口： | TDMoP |
| 電路數(shù)： | 1 |
| 電源電壓： | 1.8V, 3.3V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 676-BGA |
| 供應(yīng)商設(shè)備封裝： | 676-PBGA（27x27） |
| 包裝： | 管件 |
| 其它名稱： | 90-34S13+2N0 |
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DS34S132 DATA SHEET
19-4750; Rev 1; 07/11
83 of 194
10.3 Register Definitions
In the sub-sections that follow each register definition includes a Register Type definition with 3 Type Categories:
Signal Type, Clear Type and Misc Type. The Type definition uses the form “a-b-c” where a = Signal Type, b = Clear
Type and c = Misc Type. If one of these categories is not applicable to a register bit, then an underscore, “_”, is
used (e.g. ros-cor-_).
Signal Type
ros: Read Only Status
rls:
Read Latched Status
rcs: Read Count Status
woc: Write Only Control
rwc: Read/Write Control
rod: “ros” Delayed
rld: “rls” Delayed
rcd: “rcs” Delayed
rwd: “rwc” Delayed
Clear Type
cor: Clear On Read
cow: Clear On Write
crw: Clear on Read or Write
(G.GCR.LSBCRE selected)
cnr: Clear on None or Read
(G.GCR.CCOR selected)
Misc Type
ix:
Interrupt level “x”
(x = 1, 2 or 3)
sc:
Saturating Counter
nc:
Non-saturating Counter
The term “Delayed” means that the Read or Write operation does not complete within one clock cycle and the
external CPU must provide sufficient time for the operation to complete. These are RAM-based registers that do not
support immediate read/write operations. The data in this type of register is not valid until after the first Write to the
register (the data is invalid/unknown after a reset).
The term “Clear” indicates how a latch or counter is returned to its reset state. “Clear on Read” means the signal is
reset by a Read operation. For “Clear on Write”, a Write with any register value resets the register. “Clear On None”
is used by some counters to mean that the count is not reset by any action. For registers with the clear option
“crw”, the global G.GCR.LSBCRE bit selects between “Clear On Read” and “Clear On Write”. For registers with the
clear option “cnr”, the global G.GCR.CCOR bit selects between “Clear On Read” and “Clear On None”.
Saturating Counters stop incrementing at their maximum count. Non-saturating counters roll-over back to “zero”
after they reach their maximum count.
The “x” that is used in the “ix” Type means that the interrupt level may be any of x = 1 to 3, where 1 is lowest level
interrupt in the S132 interrupt hierarchy (e.g. roi1). All interrupt generating registers have an associated register that
is used to enable or disable (mask) the interrupt.
The “Description” term “Reserved” means that this bit has only one valid setting. The bit name in the far left column
may be “RSVD” or some other name (e.g. “CCRSTDP”). In most cases, the only valid setting is the default value. In
a few cases (as noted) they use a non-default value that is indicated in the Description column (e.g. Reserved
. This
must be programmed to “1”.)
Numbers are written in decimal notation unless a “b” suffix is used for binary (e.g. 010b) or a “0x” prefix or “h” suffix
is used for hexadecimal (e.g. “0x4F” or “0800h”; the “0x” and ‘h” notation have the same meaning).
Yellow shading is used to identify the 32-bit register name and characteristics. White (non-shaded) rows are used
to define the bit field s within each 32-bit register.
10.3.1 Global Registers (G.)
10.3.1.1 Global Configuration Registers (G.)
Table 10-3. Global Configuration Registers
G. Field
Name
Addr (A:)
Bit [x:y] Type
Description
IDR.
A:0000h
ID Register. Default: 00.0J.JJh where J = JTAG ID
ID
[31:20] ros-_-_
ID. Reserved
ID
[19:4] ros-_-_
ID. Same information as the lower 16 bits of JTAG CODE ID portion of the JTAG
ID register. JTAG ID[27:12].
ID
[3:0] ros-_-_
Originial Rev ID. Was not modified to reflect Rev A2 ID. Still reads 4’b0000.
GCR.
A:0004h
Global Configuration Register. Default: 0x00.00.08.00
RSVD
[31:28]
Reserved.
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相關(guān)代理商/技術(shù)參數(shù) |
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| DS34S132GN+ | 功能描述:通信集成電路 - 若干 32Port TDM-Over-Pack Transport Device RoHS:否 制造商:Maxim Integrated 類型:Transport Devices 封裝 / 箱體:TECSBGA-256 數(shù)據(jù)速率:100 Mbps 電源電壓-最大:1.89 V, 3.465 V 電源電壓-最小:1.71 V, 3.135 V 電源電流:50 mA, 225 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Tube |
| DS34S132GNA2+ | 功能描述:通信集成電路 - 若干 32Port TDM-Over-Pack Transport Device RoHS:否 制造商:Maxim Integrated 類型:Transport Devices 封裝 / 箱體:TECSBGA-256 數(shù)據(jù)速率:100 Mbps 電源電壓-最大:1.89 V, 3.465 V 電源電壓-最小:1.71 V, 3.135 V 電源電流:50 mA, 225 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Tube |
| DS34T101 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Single/Dual/Quad/Octal TDM-over-Packet Chip |
| DS34T101_08 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Single/Dual/Quad/Octal TDM-over-Packet Chip |
| DS34T101_09 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Single/Dual/Quad/Octal TDM-over-Packet Chip |
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