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| 型號(hào)： | DS34S132GN+ |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 122/194頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC TDM OVER PACKET 676-BGA |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 40 |
| 功能： | TDM-over-Packet（TDMoP） |
| 接口： | TDMoP |
| 電路數(shù)： | 1 |
| 電源電壓： | 1.8V, 3.3V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 676-BGA |
| 供應(yīng)商設(shè)備封裝： | 676-PBGA（27x27） |
| 包裝： | 管件 |
| 其它名稱： | 90-34S13+2N0 |
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DS34S132 DATA SHEET
19-4750; Rev 1; 07/11
33 of 194
In general, the DCR technique provides better clock recovery performance than the ACR technique (when
compared using an equal quality synclk reference input for both techniques).
For DCR applications the PW standards assume both ends of the PW use the same frequency for a DCR common
clock reference. The S132 however also allows the DCR common clock frequency to differ from one end to the
other (e.g. 2.5 MHz at one end and 25 MHz at the other), but with the requirement that the two are frequency
locked to the same source (e.g. BITS) and the S132 is programmed to compensate for the frequencies that are
used (Pn.PRCR4 and Pn.PRCR5).
To function well the DCR common clock (CMNCLK) frequency must be an integer multiple of 8 KHz and in the
range of 1 MHz to 25 MHz, but not close to the T1/E1 clock frequency (1.544 MHz or 2.048 MHz). The CMNCLK
frequency can be in the range from 8 KHz to 1 MHz, but with degraded MTIE (Maximum Time Interval Error)
performance. The following frequencies are recommended according to equipment type. The RTP Timestamp
coefficient registers (Pn.PRCR4 and Pn.PRCR5) must be set according to the CMNCLK frequency that is used.
SONET/SDH based equipment – 19.44 MHz
ATM network equipment – 9.72 MHz or 19.44 MHz
GPS based equipment – 8.184 MHz
Ethernet Equipment – 25 MHz
An internal CLAD generates the internal synclk signal from REFCLK or CMNCLK (selected with G.CCR.SCS). Any
of the input frequencies listed below can be used. The input frequency is selected using G.CCR.FS.
5.000 MHz
5.120 MHz
10.00 MHz
10.24 MHz
12.80 MHz
13.00 MHz
19.44 MHz
20.00 MHz
25.00 MHz
30.72 MHz
38.80 MHz
77.76 MHz
155.52 MHz
The S132 includes 32 Clock Recovery Engines that are each hardwired to one of the 32 TDM Ports. One of the 32
TDM Port recovered clocks (aclk_n; n = 0 to 31) can be assigned as a Global Clock Recovery reference (grclk)
using G.GCR.GRCSS. This allows the Clock Recovery Engine for one TDM Port to act as the “master timing” for
other “slave timed” TDM Ports.
An LIUCLK output is generated by the CLAD to provide an optional T1/E1 clock reference for external circuits. The
output is enabled with G.CCR.LCE and the frequency is set using G.CCR.LCS (1.544 MHz or 2.048 MHz).
In the TXP direction, the rate at which TXP Packets are transmitted is always directly related to the rate at which
data is received at the TDM Port. In the RXP direction, there are several methods that can be used to reconstruct
the transmit T1/E1 timing. The multiple timing sources provide the ability to support several different timing
applications and to provide primary and secondary (backup) timing.
In the RXP direction, the TCLKOn signal can derive its timing from RCLKn (the TDM Port receive clock input),
EXTCLK0, EXTCLK1, the internal aclk_n signal (the recovered clock from the Port “n” Clock Recovery Engine) or
the internal grclk signal (Global Recovered Clock that is selected by G.GCR.GRCSS). Only aclk_n and grclk derive
their timing from received RXP Packets. The selected timing source for a TDM Port must be equal to the payload
bit rate of each of the RXP Bundles assigned to that TDM Port. If the timing of the selected clock source differs
from one of its Bundles, then the internal RXP Jitter Buffer for that Bundle will overflow or underrun.
A TDM Port can be timed to an external T1/E1 reference that is input at EXTCLK0 or EXTCLK1 (e.g. for a Network
Timed T1/E1). If the synclk reference input (at REFCLK or CMNCLK) is from a Network Timing source (e.g. BITS 8
KHz), then the LIUCLK output can be tied to EXTCLK0 or EXTCLK1 to provide Network Timing to the TDM Port.
RCLKn can be used as the TCLKOn timing source in applications where the TDM Port must use “Loop Timing”.
“Loop Timing” can be used when the TXP data stream at any node within the network returns the TXP data back in
the RXP direction (loopback). Or it can be used in applications where the local transmit T1/E1 line rate is required
to use the local receive T1/E1 line rate (e.g. RCLKn provides Network Timing).
9.2.1.1 PW-Timing
The TDMoP PW standards define two PW Timing techniques: “Adaptive Clock Recovery” (ACR) and “Differential
Clock Recovery using Differential Timestamps” (DCR-DT). A third technique, using “Absolute Timestamps” (AT), is
supported by some companies, but is not prescribed by the TDMoP standards. The S132 is compatible with each
of these PW-Timing techniques.
The ACR technique uses the (intrinsic) packet transmission rate to convey the PW-Timing (e.g. 1 packet received
every 1 ms). The DCR technique uses RTP Timestamps to convey the PW-Timing information from the originating
side. Differential RTP Timestamps (DCR-DT) provide a means to monitor the time period between successive
packets using time units that are equalized at both ends of the PW through the use of a common clock reference
signal (e.g. Timestamp = 125 might equate to 125 us). The “Absolute RTP Timestamp” (AT) indicates the amount
of data that has been received at the TDM Port (e.g. 1000 bits) making the Absolute Timestamp an integer multiple
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| DS34S132GN+ | 功能描述:通信集成電路 - 若干 32Port TDM-Over-Pack Transport Device RoHS:否 制造商:Maxim Integrated 類型:Transport Devices 封裝 / 箱體:TECSBGA-256 數(shù)據(jù)速率:100 Mbps 電源電壓-最大:1.89 V, 3.465 V 電源電壓-最小:1.71 V, 3.135 V 電源電流:50 mA, 225 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Tube |
| DS34S132GNA2+ | 功能描述:通信集成電路 - 若干 32Port TDM-Over-Pack Transport Device RoHS:否 制造商:Maxim Integrated 類型:Transport Devices 封裝 / 箱體:TECSBGA-256 數(shù)據(jù)速率:100 Mbps 電源電壓-最大:1.89 V, 3.465 V 電源電壓-最小:1.71 V, 3.135 V 電源電流:50 mA, 225 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Tube |
| DS34T101 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Single/Dual/Quad/Octal TDM-over-Packet Chip |
| DS34T101_08 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Single/Dual/Quad/Octal TDM-over-Packet Chip |
| DS34T101_09 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Single/Dual/Quad/Octal TDM-over-Packet Chip |
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