19-4750; Rev1; 7/11 23 of 194 Pin Name Type Pin Description RXD[7:0] I Receive Data 0 through 7(GMII Mode – RXD[" />
參數(shù)資料
型號: DS34S132GN+
廠商: Maxim Integrated Products
文件頁數(shù): 111/194頁
文件大?。?/td> 0K
描述: IC TDM OVER PACKET 676-BGA
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 40
功能: TDM-over-Packet(TDMoP)
接口: TDMoP
電路數(shù): 1
電源電壓: 1.8V, 3.3V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 676-BGA
供應(yīng)商設(shè)備封裝: 676-PBGA(27x27)
包裝: 管件
其它名稱: 90-34S13+2N0
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁當(dāng)前第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁
DS34S132 DATA SHEET
19-4750; Rev1; 7/11
23 of 194
Pin Name
Type Pin Description
RXD[7:0]
I
Receive Data 0 through 7(GMII Mode – RXD[0:7]). Eight bits of received data,
sampled synchronously with the rising edge of RXCLK. For every clock cycle, the
PHY transfers 8 bits to the device. RXD[0] is the least significant bit of the data. Data
is not considered valid when RXDV is low.
Receive Data 0 through 3(MII Mode – RXD[0:3]). Four bits of received data,
sampled synchronously with RXCLK. Accepted when CRS is asserted. When MII
mode is selected, RXD[4:7] pins are not used.
RXDV
I
Receive Data Valid (GMII). This active high signal, synchronous to RXCLK, indicates
valid data from the PHY. In GMII mode the data RXD[0:7] is ignored if RXDV is not
asserted high.
Receive Data Valid (MII). This active high signal, synchronous to RXCLK, indicates
valid data from the PHY. In MII mode the data RXD[0:3] is ignored if RXDV is not
asserted high.
RXER
I
Receive Error (GMII). This signal indicates a receive error or a carrier extension in
the GMII Mode.
Receive Error (MII). Asserted by the PHY for one or more RXCLK periods indicating
that an error has occurred. Active high indicates receive packet is invalid.
MII and GMII modes: This is synchronous with RXCLK.
COL
I
Collision Detect (MII). Asserted by the Ethernet PHY to indicate that a collision is
occurring. This signal is only valid in half duplex mode, and is ignored in full duplex
mode.
CRS
I
Receive Carrier Sense. This signal is asserted by the PHY when either transmit or
receive medium is active. This signal is not synchronous to any of the clocks.
MDC
Oz
Management Data Clock. A divided down SYSCLK that clocks management data to
and from the PHY.
MDIO
IO
Management Data IO. Data path for control information between the device and the
PHY. Pull to logic high externally through a 1.5K ohm resistor. The MDC and MDIO
pins are used to write or read up to 32 Control and Status Registers in PHY
Controllers. This port can also be used to initiate Auto-Negotiation for the PHY.
CPU Interface
PD[31:0]
IO
32-bit Processor Data Bus. PD[31] is the MSB which should be mapped to D[0] of a
MPC8xxx processor.
16-bit Processor Data Bus. PD[15] is the MSB which should be mapped to D[0] of a
MPC8xxx processor. PD[31:16] is not used and should be tied low.
32-bit & 16-bit Processor Data Bus. Input signals on this bus are captured by the
rising edge of SYSCLK. Output signals are updated on the rising edge of SYSCLK.
PA[13:2]
I
Processor Address Bus. The signals on this bus are captured by the rising edge of
SYSCLK.
PA[1]
I
32-bit Processor Address Bus Bit 1. PA[1] is not used and should be tied low.
32-bit Processor Address Bus Bit 1. When PA[1] = 0, PD[15:0] carries the upper 16
bits of the 32-bit word. When PA[1] = 1, PD[15:0] carries the lower 16 bits of the 32-bit
word.
PALE
I
Processor Address Latch. PALE latches PA[13:1] on its falling edge. In non-muxed
mode, tie high.
PCS_N
I
Processor Chip Select. Processor chip select active low. Synchronous to SYSCLK.
PRW
I
Processor Read/Write. The behavior of this signal is described by PRWCTRL. This
signal is synchronous to SYSCLK.
相關(guān)PDF資料
PDF描述
DS34T102GN+ IC TDM OVER PACKET 484TEBGA
DS3501U+H IC POT NV 128POS HV 10-USOP
DS3502U+ IC POT DGTL NV 128TAP 10-MSOP
DS3503U+ IC POT DGTL NV 128TAP 10-MSOP
DS3897MX IC TXRX BTL TRAPEZIODAL 20-SOIC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS34S132GN+ 功能描述:通信集成電路 - 若干 32Port TDM-Over-Pack Transport Device RoHS:否 制造商:Maxim Integrated 類型:Transport Devices 封裝 / 箱體:TECSBGA-256 數(shù)據(jù)速率:100 Mbps 電源電壓-最大:1.89 V, 3.465 V 電源電壓-最小:1.71 V, 3.135 V 電源電流:50 mA, 225 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Tube
DS34S132GNA2+ 功能描述:通信集成電路 - 若干 32Port TDM-Over-Pack Transport Device RoHS:否 制造商:Maxim Integrated 類型:Transport Devices 封裝 / 箱體:TECSBGA-256 數(shù)據(jù)速率:100 Mbps 電源電壓-最大:1.89 V, 3.465 V 電源電壓-最小:1.71 V, 3.135 V 電源電流:50 mA, 225 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Tube
DS34T101 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Single/Dual/Quad/Octal TDM-over-Packet Chip
DS34T101_08 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Single/Dual/Quad/Octal TDM-over-Packet Chip
DS34T101_09 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Single/Dual/Quad/Octal TDM-over-Packet Chip