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參數(shù)資料
| 型號(hào)： | DS34S132GN+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 113/194頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TDM OVER PACKET 676-BGA |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 40 |
| 功能： | TDM-over-Packet（TDMoP） |
| 接口： | TDMoP |
| 電路數(shù)： | 1 |
| 電源電壓： | 1.8V, 3.3V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 676-BGA |
| 供應(yīng)商設(shè)備封裝： | 676-PBGA（27x27） |
| 包裝： | 管件 |
| 其它名稱： | 90-34S13+2N0 |
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DS34S132 DATA SHEET
19-4750; Rev1; 7/11
25 of 194
Pin Name
Type Pin Description
Clocks, Resets , JTAG & Miscellaneous
CMNCLK
I
Common Clock. This clock is used for Differential Clock Recovery. Common clock
has to be a multiple of 8 kHz and in the range of 8 kHz to 25 MHz. The frequency
input should not be too close to an integer multiple of the service clock frequency.
Based on these criteria, the following frequencies are suggested:
SONET/SDH systems: 19.44 MHz
ATM systems: 9.72 MHz or 19.44 MHz
GPS systems: 8.184 MHz
Synchronous Ethernet systems: 25 MHz
CMNCLK may also be used in lieu of REFCLK if the CMNCLK frequency matches
one of the frequencies used for REFCLK and if CMNCLK is a high quality clock
(Stratum 3). When CMNCLK is not used tie to ground or VDD(3.3V).
EXTCLK[1:0]
I
External Clock. This clock is used as an E1 or T1 Station Clock. In this mode, is
used for TDATn. When this clock is not used tie to ground or VDD(3.3V).
SYSCLK
I
System Clock. This clock shall be in the range of 50 – 85 MHz and also synchronous
with the CPU’s bus clock.
LIUCLK
O
LIU Clock. This clock is generated by the CLAD based on either REFCLK or
CMNCLK and can be selected to be 1.544 MHz or 2.048 MHz. By default, this clock
drives low.
REFCLK
I
Reference Clock. This clock must be one of the following frequencies: 5 MHz, 5.12
MHz, 10 MHz, 10.24 MHz, 12.8 MHz, 13 MHz, 19.44 MHz, 20 MHz, 25 MHz, 30.72
MHz, 38.88 MHz, 77.76 MHz, or 155.52 MHz. This input shall be a stratum 3 quality
or better. This clock is selectable by the CLAD to derive the synthesis clock for the
clock recovery engine. CMNCLK can be used in lieu of REFCLK.
ETHCLK
I
Ethernet Clock. This clock is used as the source for the GTXCLK in GMII mode and
is used as a constant reference for several internal clocks. This signal must always be
provided with 125MHz clock +/- 100ppm. It may use the same oscillator as DDRCLK.
DDRCLK
I
DDR Clock. This clock is used as the source for SD0CLK and SDCLK. The clock
frequency should be 125 MHz. It may use the same oscillator as ETHCLK.
RST_N
I
Reset. An active low signal on this pin resets the internal registers and logic. While
this pin is held low, the microprocessor interface is kept in a high-impedance state.
This pin should remain low until power is stable and then set high for normal
operation.
JTCLK
I
JTAG Clock. This signal is used to shift data into JTDI on the rising edge and out of
JTDO on the falling edge.
JTMS
Ipu
JTAG Mode Select. This pin is sampled on the rising edge of JTCLK and is used to
place the test access port into the various defined IEEE 1149.1 states. This pin has a
10k pull up resistor.
JTDI
Ipu
JTAG Data In. Test instructions and data are clocked into this pin on the rising edge
of JTCLK. This pin has a 10k pull up resistor.
JTDO
Oz
JTAG Data Out. Test instructions and data are clocked out of this pin on the falling
edge of JTCLK. If not used, this pin should be left unconnected.
JTRST_N
Ipu
JTAG Reset. JTRST is used to asynchronously reset the test access port controller.
After power up, a rising edge on JTRST will reset the test port and cause the device
I/O to enter the JTAG DEVICE ID mode. Pulling JTRST low restores normal device
operation. JTRST is pulled HIGH internally via a 10k resistor operation. If boundary
scan is not used, this pin should be held low.
TEST_N
I
Test Enable. (active low)
HIZ_N
I
High Impedance test enable. This signal puts all digital output and bi-directional pins
in the high impedance state when it is low and JTRST is low. For normal operation tie
high. This is an asynchronous input.
EXTINT
I
External PHY Interrupt. PHY Interrupt to MAC, if MDIO and MDC are not used.
MT[15:0]
IO
Manufacturing Test. For normal operation leave these pins unconnected.
SMTI
Ipu
Manufacturing Test Input, Must be tied to VCC33.
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| DS34S132GN+ | 功能描述:通信集成電路 - 若干 32Port TDM-Over-Pack Transport Device RoHS:否 制造商:Maxim Integrated 類型:Transport Devices 封裝 / 箱體:TECSBGA-256 數(shù)據(jù)速率:100 Mbps 電源電壓-最大:1.89 V, 3.465 V 電源電壓-最小:1.71 V, 3.135 V 電源電流:50 mA, 225 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Tube |
| DS34S132GNA2+ | 功能描述:通信集成電路 - 若干 32Port TDM-Over-Pack Transport Device RoHS:否 制造商:Maxim Integrated 類型:Transport Devices 封裝 / 箱體:TECSBGA-256 數(shù)據(jù)速率:100 Mbps 電源電壓-最大:1.89 V, 3.465 V 電源電壓-最小:1.71 V, 3.135 V 電源電流:50 mA, 225 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Tube |
| DS34T101 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Single/Dual/Quad/Octal TDM-over-Packet Chip |
| DS34T101_08 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Single/Dual/Quad/Octal TDM-over-Packet Chip |
| DS34T101_09 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Single/Dual/Quad/Octal TDM-over-Packet Chip |
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