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參數(shù)資料
| 型號(hào)： | DS34S132GN+ |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 147/194頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC TDM OVER PACKET 676-BGA |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 40 |
| 功能： | TDM-over-Packet（TDMoP） |
| 接口： | TDMoP |
| 電路數(shù)： | 1 |
| 電源電壓： | 1.8V, 3.3V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 676-BGA |
| 供應(yīng)商設(shè)備封裝： | 676-PBGA（27x27） |
| 包裝： | 管件 |
| 其它名稱： | 90-34S13+2N0 |
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DS34S132 DATA SHEET
19-4750; Rev 1; 07/11
56 of 194
The DB.BCR register is used to program the Packet BERT Monitor for New Test Pattern Load (RNPL), Test Pattern
Inversion (RPIC), Manual Resynchronization (MPR) and Pattern Resynchronization Disable (APRD).
The DB.BSR, DB.BSRL, DB.BSRIE, DB.RBECR, DB.RBCR are used to Monitor the Packet BERT Test status.
The Packet BERT Generator can be programmed to insert errors in the BERT Test Pattern using the EB.TEICR
register. This can be used to demonstrate that the monitoring function (local or far end) is functioning properly.
Receive and transmit TDM Port Timeslot functions, for Bundles that have been assigned to a Packet BERT Test,
continue to function when a Packet BERT Test has been enabled except that the received TDM Port Timeslot data
for the TXP Bundle that is assigned to the Packet BERT Test is replaced by the Packet BERT Test Pattern. For
most applications the TDM Port Timeslots should be disabled during a Packet BERT Test.
Special Consideration
CAS Signaling functions should be disabled for a Bundle that is used for Ethernet BERT Testing.
9.3.2 RXP Packet Classification
The header for a packet commonly contains several different header fields. The Classifier iteratively steps through
each field of the header, looking for recognized formats and values. When the Classifier detects a recognized
format/value, the Classifier either continues the classification process or has sufficient information to forward the
packet to the next internal circuit block. Programmed settings determine the outcome for each interpretive step and
are described in this section at a functional level. Figure 9-23 depicts the various destinations for RXP Packets.
Figure 9-23. RXP Packet Classifier Environment
DS34S132
Ethernet
MAC
SAT/CES Connection
HDLC Connection
Timing Connection
Payload sent to Buffer Manager Jitter
Buffer for RXP SAT/CES Engine
Payload sent to Buffer Manager
for RXP HDLC Engine
Timing information sent to
RXP Clock Recovery Engine
CPU Connection
Discard
RXP Pkt
Classifier
Pkt sent to Buffer Manager TXP CPU Queue
When the Classifier determines that the format of a received RXP Packet header is not recognized, the packet may
be discarded or forwarded to the CPU depending on the packet format and programmed settings. The program
settings that determine Discard vs. CPU for unrecognized format/values are referred to as Discard Switches. These
are described in the CPU Packet Classification section.
9.3.2.1 Generalized Packet Classification
The Classifier can be programmed to recognize 2 Ethernet DAs (PC.CR17 – PC-CR19) and the Ethernet
Broadcast Address. If a received Ethernet DA is not equal to one of these values the packet is either forwarded to
the CPU or discarded (PC.CR1.DPS9).
To be accepted an RXP Packet must use the DIX/Ethernet II or IEEE 802 LLC/SNAP format and can include 0, 1,
or 2 VLAN tags. If VLAN tags are included, the inner VLAN tag TPID must equal PC.CR3.VITPID (normally 0x8100
for CVLAN). When a packet includes 2 VLAN tags the outer VLAN TPID must equal PC.CR3.VOTPID (for SVLAN).
The next packet header field that is tested is the Ethernet Type. The Classifier tests the Ethernet Type to determine
if the packet uses a recognized PW Header. Six PW Headers can be recognized: MEF-8, MFA-8, UDP/IPv4,
UDP/IPv6, L2TPv3/IPv4 and L2TPv3/IPv6.
For UDP and L2TPv3 applications, the Ethernet Type field must either be equal to IPv4 or IPv6. The S132 can be
programmed to only recognize IPv4, only recognize IPv6 or to recognize both IPv4 and IPv6 (PC.CR1.RXPIVS and
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS34S132GN+ | 功能描述:通信集成電路 - 若干 32Port TDM-Over-Pack Transport Device RoHS:否 制造商:Maxim Integrated 類型:Transport Devices 封裝 / 箱體:TECSBGA-256 數(shù)據(jù)速率:100 Mbps 電源電壓-最大:1.89 V, 3.465 V 電源電壓-最小:1.71 V, 3.135 V 電源電流:50 mA, 225 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Tube |
| DS34S132GNA2+ | 功能描述:通信集成電路 - 若干 32Port TDM-Over-Pack Transport Device RoHS:否 制造商:Maxim Integrated 類型:Transport Devices 封裝 / 箱體:TECSBGA-256 數(shù)據(jù)速率:100 Mbps 電源電壓-最大:1.89 V, 3.465 V 電源電壓-最小:1.71 V, 3.135 V 電源電流:50 mA, 225 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Tube |
| DS34T101 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Single/Dual/Quad/Octal TDM-over-Packet Chip |
| DS34T101_08 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Single/Dual/Quad/Octal TDM-over-Packet Chip |
| DS34T101_09 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Single/Dual/Quad/Octal TDM-over-Packet Chip |
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