參數(shù)資料
型號(hào)： TVP3026-220
廠商： Texas Instruments, Inc.
英文描述： Video Interface PALETTE Exract(組合像素模式視頻接口調(diào)色器)
中文描述： 視頻接口調(diào)色板Exract（組合像素模式視頻接口調(diào)色器）
文件頁數(shù)： 38/107頁
文件大小： 707K
代理商： TVP3026-220
2–24
Table 2–17. Multiplex Mode and Bus-Width Selection
MODE
SUB-
MODE
TRUE-
COLOR-
CONTROL
REGISTER
(INDEX
0x18)
MULTIPLEX-
CONTROL
REGISTER
(INDEX
0x19)
DATA
BITS
PER
PIXEL
(see
Note 3)
PIXEL
BUS
WIDTH
MULTI-
PLEX
RATIO
(see
Note 4)
OVERLAY
BITS
PER
PIXEL
TABLE
REFERENCE
(see
Note 5)
VGA
0x80
0x98
8
8
1
NA
v1
Pseud
Color
d
1
0x80
0x41
4
8
2
NA
s1
4-Bit,
Normal
0x80
0x42
4
16
4
NA
s2
0x80
0x43
4
32
8
NA
s3
0x80
0x44
4
64
16
NA
s4
2
0x80
0x61
4
8
2
NA
s5
4-Bit,
4 Bit,
Nibble
Swapped
0x80
0x62
4
16
4
NA
s6
0x80
0x63
4
32
8
NA
s7
0x80
0x64
4
64
16
NA
s8
3
0x80
0x49
8
8
1
NA
s9
0x80
0x4A
8
16
2
NA
s10
8-Bit
0x80
0x4B
8
32
4
NA
s11
0x80
0x4C
8
64
8
NA
s12
Direct-
Color
1
0x16
0x5B
24
32
4:3
NA
d1
Packed-24
Packed 24
R-G-B
8 8 8
8–8–8
0x16
0x5C
24
64
8:3
NA
d2
0x1E
0x5B
24
32
5:4
NA
d3
0x1E
0x5C
24
64
5:2
NA
d4
2
0x17
0x5B
24
32
4:3
NA
d5
Packed-24
Packed 24
B-G-R
8 8 8
8–8–8
0x17
0x5C
24
64
8:3
NA
d6
0x1F
0x5B
24
32
5:4
NA
d7
0x1F
0x5C
24
64
5:2
NA
d8
3
32-Bit
O-R-G-B
0x06
0x5B
24
32
1
8
d9
0x06
0x5C
24
64
2
8
d10
4
32-bit
B-G-R-O
0x07
0x5B
24
32
1
8
d11
0x07
0x5C
24
64
2
8
d12
NOTES:
3. Data bits per pixel is the number of bits of pixel information used as color data for each displayed pixel, often
referred to as the number of bit planes.
4. Multiplex ratio indicates the number of pixels per bus load or the number of pixels associated with each
LCLK (load clock) pulse. For example, with a 64-bit pixel bus width and 8 bit planes, each bus load is
comprised of 8 pixels. The RCLK frequency must be chosen as a function of the multiplex mode selected.
The RCLK frequency is not automatically set by mode selection; it must be set by programming the loop
clock PLL registers.
5. This column is a reference to Tables 2–18 through 2–21, where the actual manipulation of pixel information
and pixel latching sequences are illustrated for each of the multiplexing modes. For the pseudo-color pixel
latching sequence (V1 and S1 through S12) refer to Table 2–18. For the packed-24 mode pixel latching
sequence associated with the direct-color and true-color modes, refer to Table 2–19. For the direct-color
mode pixel latching sequence, refer to Table 2–20 for little-endian format and to Table 2–21 for big-endian
format.
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