參數(shù)資料
型號： TVP3026-220
廠商： Texas Instruments, Inc.
英文描述： Video Interface PALETTE Exract(組合像素模式視頻接口調(diào)色器)
中文描述： 視頻接口調(diào)色板Exract（組合像素模式視頻接口調(diào)色器）
文件頁數(shù)： 33/107頁
文件大小： 707K
代理商： TVP3026-220
2–19
2.6
The TVP3026 offers a highly versatile multiplexing scheme as illustrated in Tables 2–17 through 2–21. The
multiplexing modes allow the pixel bus (P63–P0) to be programmed to 4, 8, 16, 24, or 32 bits/pixel with pixel
bus widths ranging from 8 to 64 bits. The use of on-chip multiplexing allows graphics systems to be designed
that can support multiple pixel depths and resolutions with no hardware modification. The TVP3026 can also
be configured for pseudo-color or true-color operation.
Multiplexing of the pixel bus is controlled by and programmed through the multiplex-control register and the
true-color control register. Table 2–17 details the register settings for each mode of operation.
2.6.1
Little-Endian and Big-Endian Data Format
The TVP3026 pixel bus supports both little- and big-endian data formats for all pseudo-color, direct-color,
and true-color modes of operation. The data-format select is controlled by GCR3 of the general-control
register (see subsection 2.15.1, General Control Registers). When GCR3 is reset 0 (default), the format is
set to little endian. When GCR3 is set to 1, the format is set to big endian.
In a big-endian design, the external VRAM data bus bits must be connected in reverse order to the TVP3026
pixel bus; i.e., D63 connected to P0, D0 connected to P63, etc. This configuration connects the pixels to the
P63–P0 bus in the correct order with the first pixel to be displayed on the LSBs of the P63–P0 bus. However,
the individual bits within each pixel are now connected in bit-reversed order. When big-endian format is
selected, this bit-reversed order of each pixel is compensated for internally. The bit-reversal of pixels takes
place in groups of 4, 8, 16, or 32 bits depending on the multiplexing mode selected. This scheme enables
big-endian systems to operate in all of the available color-depths excluding the packed-24 modes.
2.6.2
VGA Modes
The VGA modes emulate the VGA modes of most personal computers. The TVP3026 has a single
configuration called VGA mode 2 to support VGA modes. VGA mode 1, which was formerly specified to
utilize the loop clock PLL with the VGA pixel port is not recommended.
VGA mode 2 supports most graphics accelerators with integrated VGA and also supports add-on graphics
boards that receive the VGA pseudo-color data from a separate VGA controller using a feature connector.
VGA mode 2 is active at power up and after reset and is fully functional without any software intervention.
VGA data and video controls are received with a synchronous VGA clock.
The feature connector configuration is emulated by many graphics accelerators with integrated VGA. In this
configuration, the pixel clock PLL is output on the RCLK terminal (bit MKC5 = 0) and sent to the accelerator’s
clock input. The clock output from the accelerator is connected to the CLK0 input of the TVP3026. The loop
clock PLL is not used. The accelerator outputs the VGA video controls and VGA7–VGA0 data synchronous
with CLK0 and, thereby, emulates the feature connector configuration. In VGA mode 2, the TVP3026 derives
the dot clock from CLK0 and latches the VGA7–VGA0 data and VGA video controls using CLK0.
To program for VGA mode 2, bit MCR7 in the multiplex control register must be set to 1 to select VGA mode,
and bit MCR6 must be reset to 0 to latch VGA7–VGA0 and the VGA video controls with CLK0. The clock
selection register bits CSR3–CSR0 must be set as 0111 for CLK0 data latching.
2.6.3
Pseudo-Color Mode
In pseudo-color mode (sometimes called color indexing), the pixel-bus inputs address the palette RAM. The
pallete RAM functions as a color look-up table. The data in each RAM location is comprised of 24 bits, 8
bits for each of the red, green, and blue color DACs. The pseudo-color mode is further grouped into 3
submodes, depending on the data bits per pixel. In each submode, a pixel bus width of 8, 16, 32 or 64 bits
may be used. Data should always be presented on the least significant bits of the pixel bus. For example,
when a 16-bit pixel bus width is used, the pixel data must be presented on P15–P0. See Tables 2–17 and
2–18 for more details.
Submode 1 uses four bit planes to address the color palette. The four bits are fed into the low-order address
bits of the palette with the four high-order address bits being defined by the palette-page register. This mode
provides 16 pages of 16 colors and can be used at multiplex ratios of 2:1 to 16:1.
Multiplexing Modes of Operation
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PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TVP3026-220AMDN 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette
TVP3026-220APCE 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette
TVP3026-220BMDN 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette
TVP3026-220BPCE 制造商:Rochester Electronics LLC 功能描述:- Bulk
TVP3026-220MDN 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC)
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