參數(shù)資料
型號(hào): TVP3026-220
廠商: Texas Instruments, Inc.
英文描述: Video Interface PALETTE Exract(組合像素模式視頻接口調(diào)色器)
中文描述: 視頻接口調(diào)色板Exract(組合像素模式視頻接口調(diào)色器)
文件頁(yè)數(shù): 24/107頁(yè)
文件大?。?/td> 707K
代理商: TVP3026-220
2–10
2.4.2
The memory clock (MCLK) PLL may be used at frequencies up to 100 MHz. Appendix A provides optimal
register values for all frequencies that can be synthesized using the common 14.31818 MHz reference. The
MCLK PLL maximum output frequency of 100 MHz may not be exceeded. The equations for the VCO
frequency and for the PLL output frequency are the same as for the pixel clock PLL.
Memory Clock PLL
Provided:
FVCO
8
FREF
65
65
M
N
Minimum VCO Frequency
FVCO
Maximum VCO Frequency
(3)
Then the PLL output frequency is :
FPLL
FVCO
2P
(4)
The N-, M-, and P-value registers may be programmed to any value within the following limits:
40
1
0
N(5–0)
M(5–0)
P(1,0)
62
62
3
The bit assignments of the N-, M-, and P-value and the status register for the MCLK PLL are given in
Table 2–12. The bits shown as 0 or 1 must be written with these fixed values. PLLEN resets the PLL with
0 and enables the PLL to oscillate when set to 1. When set to 1, the LOCK status bit indicates that the PLL
has locked to the selected frequency. The remaining status register bits are for test purposes. The MCLK
PLL and loop clock PLL are further controlled by the MCLK/loop clock control register shown in Table 2–13.
Table 2–12. MCLK PLL Registers
REGISTER
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
N value
1
1
N5
N4
N3
N2
N1
N0
M value
0
0
M5
M4
M3
M2
M1
M0
P value
PLLEN
0
1
1
0
0
P1
P0
Status
X
LOCK
X
X
X
X
X
X
X = do not care
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TVP3026-220AMDN 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette
TVP3026-220APCE 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette
TVP3026-220BMDN 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette
TVP3026-220BPCE 制造商:Rochester Electronics LLC 功能描述:- Bulk
TVP3026-220MDN 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC)