- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄384032 > TVP3026-220 (Texas Instruments, Inc.) Video Interface PALETTE Exract(組合像素模式視頻接口調(diào)色器) PDF資料下載
參數(shù)資料
| 型號： | TVP3026-220 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Video Interface PALETTE Exract(組合像素模式視頻接口調(diào)色器) |
| 中文描述： | 視頻接口調(diào)色板Exract（組合像素模式視頻接口調(diào)色器） |
| 文件頁數(shù)： | 30/107頁 |
| 文件大?。?/td> | 707K |
| 代理商： | TVP3026-220 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁當(dāng)前第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁
2–16
Figure 2–4 shows the typical device connection for a system with VRAM clocked by the TVP3026. In this
case, the RCLK is tied back to the LCLK and this same clock drives the graphics-accelerator VGA controller
and video timing logic. If necessary, the RCLK and SCLK signals may be externally buffered within the timing
constraints (RCLK to LCLK delay) of the TVP3026. The pixel clock PLL is output on RCLK after power up.
For high resolution modes in both configurations, the pixel data is received from VRAM and the loop clock
PLL is used to adjust RCLK so that the received LCLK is aligned with the internal dot clock. The loop clock
PLL must be selected for output on the RCLK terminal. The pixel clock PLL (or an external clock source)
should be selected as the dot clock source.
Graphics
Accelerator
VRAM
VGA(7–0)
LCLK
CLK0
P(63–0)
MCLK
RCLK
TVP3026
Figure 2–3. Typical Configuration – VRAM Clocked by Accelerator
Graphics
Accelerator
VRAM
VGA(7–0)
LCLK
CLK0
P(63–0)
MCLK
RCLK
TVP3026
SCLK
Figure 2–4. Typical Configuration – VRAM Clocked by TVP3026
2.5
Frame-Buffer Interface
The TVP3026 provides two output clock signals and one input clock signal for controlling the frame-buffer
interface — SCLK, RCLK, and LCLK. The VCLK output is a division of the internal dot clock and has no
guaranteed phase relationship with RCLK. Therefore, VCLK should not be used for frame buffer interface
timing (pixel data and video controls). VCLK can drive general purpose external logic. Clocking of the frame
buffer interface is discussed in subsection 2.5.1, Frame-Buffer Clocking The 64-bit pixel bus allows many
operational display modes as defined in Section 2.6, Multiplexing Modes of Operation and Table 2–17. The
pixel latching sequence is initiated by a rising edge on LCLK. For those multiplexed modes in which multiple
pixels are latched on one LCLK rising edge, the pixel clock shifts the pixels out starting with the pixels that
reside on the low numbered pixel port terminals. For example, in an 8-bit-per-pixel pseudo-color mode with
an 8:1 multiplex ratio, the pixel display sequence is P(7–0), P(15–8), P(23–16), P(31–24), P(39–32),
P(47–40), P(55–48), and P(63–56).
The TVP3026 frame-buffer interface also supports little- and big-endian data formats on the pixel bus. This
can be controlled by general-control register (GCR) bit 3. See subsection 2.6.1, Little-Endian and
Big-Endian Data Format for details of operation.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TVP3026-250 | Video Interface PALETTE Exract(組合像素模式視頻接口調(diào)色器) |
| TX24 | 60.8 MM 5 X 8 DOT MATRIX DISPLAYS |
| TXB0102DCTR | 2-BIT BIDIRECTIONAL VOLTAGE-LEVEL TRANSLATOR WITH AUTO DIRECTION SENSING AND 【15-kV ESD PROTECTION |
| TXB0102DCTT | 2-BIT BIDIRECTIONAL VOLTAGE-LEVEL TRANSLATOR WITH AUTO DIRECTION SENSING AND 【15-kV ESD PROTECTION |
| TZX7V5D | surface mount silicon Zener diodes |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TVP3026-220AMDN | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
| TVP3026-220APCE | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
| TVP3026-220BMDN | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
| TVP3026-220BPCE | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TVP3026-220MDN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC) |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。