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參數(shù)資料
| 型號： | TVP3026-220 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Video Interface PALETTE Exract(組合像素模式視頻接口調(diào)色器) |
| 中文描述： | 視頻接口調(diào)色板Exract（組合像素模式視頻接口調(diào)色器） |
| 文件頁數(shù)： | 31/107頁 |
| 文件大?。?/td> | 707K |
| 代理商： | TVP3026-220 |
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2–17
2.5.1
The TVP3026 provides SCLK and RCLK signals, allowing for flexibility in the frame buffer interface timing.
For the pixel port (P63–P0), data is always latched on the rising edge of LCLK. If TCR5 in the true-color
control register is set to 1, use of SCLK is assumed and internal pipeline delay is added to Sync and Blank
to account for the delay in the generation of SCLK. When TCR5 bit clears to 0 (default), then this pipeline
delay is not added, and SCLK should not be used.
Frame-Buffer Clocking
2.5.2
For those systems where the color palette data latch clock (LCLK) and VRAM shift clock are generated by
the graphics controller, the TVP3026 SCLK output is not utilized. In these systems, RCLK should be
connected to the graphics controller to provide the timing reference for pixel data and video control signals.
LCLK should be a delayed version of RCLK such that the pixel data and video control signals meet the setup
and hold requirements relative to the rising edge of LCLK. LCLK may be a frequency-divided and delayed
version of RCLK as long as linear phase changes in RCLK produce linear phase changes in LCLK (and the
pixel data). Bit TCR5 in the true-color control register must be reset to 0 when SCLK is not being used, so
that additional pipeline delay in the video controls is not inserted.
Frame-Buffer Timing Without Using SCLK
The first LCLK rising edge out of blank latches the first pixel group. The last LCLK rising edge during blanking
latches the last pixel group. Figure 2–5 shows typical frame-buffer timing for this case. In Figure 2–5, the
delay from RCLK to SYSBL and P63–P0 depends on the total system loop delay through the graphics
accelerator and the VRAM. This delay may be as long as is required. It need not be less than the RCLK cycle
time.
2nd
Group
3rd
Group
4th
Group
Last Group of Pixel Data
RCLK
SYSBL
P(63–0)
Latch Last Group of Pixel Data
and SYSBL High
Latch First Group of Pixel Data
and SYSBL High
LCLK
1st
Group
Figure 2–5. Frame-Buffer Timing Without Using SCLK
2.5.3
The SCLK signal which is generated in the TVP3026 may be directly connected to VRAM, providing the shift
clock-to-clock data from VRAM into the TVP3026 pixel input port. The RCLK signal must be used as the
timing reference to clock pixel data into this port. Therefore, when SCLK is used, RCLK is typically directly
tied back to LCLK, or LCLK can be a delayed version (buffered) of RCLK within the timing requirements of
the TVP3026.
Frame-Buffer Timing Using SCLK
Operation using the SCLK timing mode must limit the RCLK-to-LCLK loop delay to the specified maximum
delay. This ensures that the relationship between the end of blanking (SYSBL active) and the first SCLK
pulse is not disturbed. When SCLK is not used, the RCLK to SCLK delay may be as long as is needed by
system logic. Figure 2–6 illustrates the frame-buffer timing using SCLK.
相關(guān)PDF資料 |
PDF描述 |
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| TVP3026-250 | Video Interface PALETTE Exract(組合像素模式視頻接口調(diào)色器) |
| TX24 | 60.8 MM 5 X 8 DOT MATRIX DISPLAYS |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TVP3026-220AMDN | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
| TVP3026-220APCE | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
| TVP3026-220BMDN | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
| TVP3026-220BPCE | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TVP3026-220MDN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC) |
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