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參數(shù)資料
| 型號： | TVP3026-220 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Video Interface PALETTE Exract(組合像素模式視頻接口調(diào)色器) |
| 中文描述： | 視頻接口調(diào)色板Exract（組合像素模式視頻接口調(diào)色器） |
| 文件頁數(shù)： | 14/107頁 |
| 文件大?。?/td> | 707K |
| 代理商： | TVP3026-220 |
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1–8
1.5
Terminal Functions (Continued)
TERMINAL
I/O
DESCRIPTION
NAME
NO.
105
SFLAG
I
Split shift register transfer flag. A high pulse on SFLAG during blanking is passed
directly to the SCLK terminal. This operation is available to meet the special serial
clocking requirements of some VRAM devices. When SFLAG is not used,
SFLAG should be connected to GND.
SYSBL
101
I
System blank input. SYSBL is active low. This should be selected for all modes
other than VGA mode 2. This signal is pipeline delayed before being passed to
the DACs.
SYSHS,
SYSVS
99, 100
I
System horizontal and vertical sync inputs. These signals should be selected for
all modes other than VGA mode 2. These signals are pipeline delayed and each
may be inverted before being passed to the HSYNCOUT and VSYNCOUT
terminals. General control register bits GCR(1,0) control the polarity inversion.
When used to generate the sync level on the green current output, SYSHS and
SYSVS must be active low at the input to the TVP3026.
VCLK
125
O
Programmable auxiliary clock output. VCLK is derived from the internal dot clock
using a programmable divide ratio and does not utilize the loop clock PLL for
synchronization. Since pixel data and video controls are always referenced to
RCLK and LCLK (or CLK0), use of VCLK for the frame buffer interface or video
timing is not recommended.
VGABL
104
I
VGA blank input. VGABL is active low. This should be selected when in VGA
mode 2 (CLK0 latching of VGA data and video controls). VGABL is pipeline
delayed before being passed to the DACs.
VGAHS,
VGAVS
102, 103
I
VGA horizontal and vertical sync inputs. These signals should be used when in
VGA mode 2 (CLK0 latching of VGA data and video controls). These signals are
pipeline delayed and each may be inverted before being passed to the
HSYNCOUT and VSYNCOUT terminals. General control register bits GCR(1,0)
control the polarity inversion. When used to generate the sync level on the green
current output, VGAHS and VGAVS must be active low at the input to the
TVP3026.
VGA7–VGA0
88–95
I
VGA port. This bus can be selected as the pixel input bus for VGA modes, but
it does not allow for any multiplexing.
WR
43
I
Write strobe input. A low signal on WR initiates a write to the register map. Write
transfer data is latched from the D(7–0) bus with the rising edge of WR.
XTAL1,
XTAL2
119, 120
I/O
Connections for quartz crystal resonator. XTALx is a reference for the frequency
synthesis PLLs. XTAL2 may be used as a TTL reference clock input, in which
case XTAL1 is left unconnected.
8/6
98
I
DAC resolution selection. This terminal is used to select the data bus width (8 or
6 bits) for the DACs and is provided for VGA downward compatibility. When the
8/6 signal is high, 8-bit bus transfers are used with D7 the MSB and D0 the LSB.
For 6-bit bus operation, while the color palette RAM still has the 8-bit information,
the data is shifted to the upper six bits and the two LSBs are filled with zeros at
the output multiplexer to the DACs. The palette RAM data register zeroes the two
MSBs when the palette RAM is read in the 6-bit mode. The function of this
terminal may be overridden in software. When not used, the 8/6 terminal should
be connected to GND so that 6-bit VGA operation begins at power up.
NOTE 1: All unused inputs should be tied to a logic level and not allowed to float.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TVP3026-220AMDN | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
| TVP3026-220APCE | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
| TVP3026-220BMDN | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
| TVP3026-220BPCE | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TVP3026-220MDN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC) |
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