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參數(shù)資料
| 型號： | TVP3026-220 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Video Interface PALETTE Exract(組合像素模式視頻接口調(diào)色器) |
| 中文描述： | 視頻接口調(diào)色板Exract（組合像素模式視頻接口調(diào)色器） |
| 文件頁數(shù)： | 13/107頁 |
| 文件大?。?/td> | 707K |
| 代理商： | TVP3026-220 |
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1–7
1.5
Terminal Functions (Continued)
TERMINAL
I/O
DESCRIPTION
NAME
NO.
97
PSEL
I
Port select. PSEL provides the capability of switching between direct color and
true color or overlay. Multiple true color or overlay windows may be displayed
using the PSEL control. Since PSEL is sampled with LCLK, the granularity for
switching depends on the number of pixels loaded per LCLK. When PSEL is not
used, it should be connected to GND.
P63–P0
3–16,
19–38,
110–116,
127–135,
138–141,
149–158
I
Pixel input port. The port can be used in various modes as described in
Section 2.6, Multplexing Modes of Operation. Unused terminals should not be
allowed to float.
RCLK
124
O
Reference clock output. RCLK can be programmed to output either the pixel clock
PLL (power up default) or the loop clock PLL. The pixel clock PLL is selected to
provide a reference clock to the VGA controller. In this configuration, the VGA
controller returns VGA data and video controls along with a synchronous clock
which becomes the TVP3026 dot clock source using CLK0. For all other modes,
the loop clock PLL is selected to provide the reference clock. In this configuration,
the pixel clock PLL (or external clock) becomes the TVP3026 dot clock source.
The reference clock is used to generate VRAM shift clocks (or clocks a VGA
controller) and generate video controls. The pixel port (or VGA port) and video
controls are latched by LCLK. The loop clock PLL controls the phase of RCLK to
phase-lock the received LCLK with the internal dot clock.
For systems that use SCLK as the VRAM shift clock, RCLK should be connected
to LCLK. An external buffer may be used between RCLK and LCLK when SCLK
is also buffered, within the timing constraints of the TVP3026. RCLK is not gated
off during blanking.
REF
78
I/O
Voltage reference for DACs. An internal voltage reference of nominally 1.235 V
is provided that requires an external 0.1-
μ
F ceramic capacitor between REF and
analog GND. However, the internal reference voltage can be overdriven by an
externally-supplied reference voltage.
RESET
63
I
Master reset. All the registers assume their default state after reset. The default
state is VGA mode 2 (CLK0 latching of VGA data and video controls).
RD
44
I
Read strobe input. A low signal on RD initiates a read from the register map. Read
transfer data is enabled onto the D(7–0) bus when RD is low (see
Figure 3–1).
RS3–RS0
42, 55–57
I
Register select inputs. These terminals specify the location in the direct register
map that is to be accessed as shown in Table 2–1.
SCLK
126
O
Shift clock output. SCLK is a gated version of the loop clock PLL output and is
gated off during blanking. SCLK may drive the VRAM shift clock directly. This is
intended for designs in which the graphics controller does not supply the VRAM
shift clock.
SENSE
64
O
Test mode DAC comparator output signal. SENSE is low when one or more of the
DAC output analog levels is above the internal comparator reference of
350 mV
±
50 mV.
NOTE 1: All unused inputs should be tied to a logic level and not allowed to float.
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PDF描述 |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| TVP3026-220AMDN | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
| TVP3026-220APCE | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
| TVP3026-220BMDN | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
| TVP3026-220BPCE | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TVP3026-220MDN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC) |
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