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參數(shù)資料
| 型號： | TVP3026-220 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Video Interface PALETTE Exract(組合像素模式視頻接口調(diào)色器) |
| 中文描述： | 視頻接口調(diào)色板Exract（組合像素模式視頻接口調(diào)色器） |
| 文件頁數(shù)： | 19/107頁 |
| 文件大?。?/td> | 707K |
| 代理商： | TVP3026-220 |
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2–5
2.2.1
To load the color palette, the MPU must first write to the color-palette RAM write address register (direct
register: 0000) with the address where the modification is to start. The selected color-palette RAM location
is loaded a byte at a time by writing a sequence of three bytes (red, green, and blue) to the palette RAM data
register (direct register: 0001). After the blue write cycle, the color-palette RAM address register increments
to the next location, which the MPU may modify by simply writing another sequence of red, green, and blue
data.
Writing to Color-Palette RAM
2.2.2
Reading from the color-palette RAM is performed by writing to the palette read address register (direct
register: 0011) with the location to be read. Three successive MPU reads from the palette RAM data register
produce red, green, and blue color data (6 or 8 bits depending on the 8/6 mode) for the specified location.
Following the blue read cycle, the address register is incremented. Since the color-palette RAM is dual
ported, the RAM may be read during active display without disturbing the video.
Reading From Color-Palette RAM
2.3
The TVP3026 VIP provides a maximum of four clock inputs (CLK0, CLK1, and CLK2/CLK2) which can be
selected as two TTL inputs and a differential ECL input or as four TTL inputs. The TTL inputs can be used
for video rates up to 140 MHz while the differential ECL can be utilized up to the device limit. At reset, CLK0
is selected as the clock source for VGA mode 2. This power-up state supports VGA pass through operation
without requiring software intervention.
Clock Selection
An alternative clock source can be selected in the clock-selection register (index: 0x1A) during normal
operation. This chosen clock input is then used as the dot clock (representing pixel rate to the monitor, see
Table 2–5).
There are two ways of using CLK0 as a clock source. When CSR(2–0) = 111, CLK0 is selected as the clock
source to generate the internal dot clock (see Table 2–6). In this mode, multiplex control register bit MCR6
must be set to 1 and only the VGA port can be used. This selects latching of VGA(7–0) and VGABL with
CLK0. When CSR(2–0) = 000, CLK0 is also selected as the clock source to generate the internal dot clock.
However, in this mode, MCR6 must be logic 0, which selects latching of VGA(7–0) and SYSBL with LCLK.
In this mode, the pixel port or the VGA port can be used.
Additionally, two crystal oscillator terminals (XTAL1, XTAL2) are provided for the integrated pixel clock and
memory clock frequency synthesis PLLs. These terminals are intended for use with a quartz crystal
resonator, but a discrete oscillator can also be utilized and input on the XTAL2 terminal (XTAL1 terminal
should be left floating in this case).
Selection of the pixel clock PLL as the pixel clock source is performed by programming the clock selection
register. In general, when the pixel clock PLL is to be selected, it should be selected after the PLL has been
programmed and allowed to achieve lock.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TVP3026-250 | Video Interface PALETTE Exract(組合像素模式視頻接口調(diào)色器) |
| TX24 | 60.8 MM 5 X 8 DOT MATRIX DISPLAYS |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TVP3026-220AMDN | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
| TVP3026-220APCE | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
| TVP3026-220BMDN | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
| TVP3026-220BPCE | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TVP3026-220MDN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC) |
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