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參數(shù)資料
| 型號： | TVP3026-220 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Video Interface PALETTE Exract(組合像素模式視頻接口調(diào)色器) |
| 中文描述： | 視頻接口調(diào)色板Exract（組合像素模式視頻接口調(diào)色器） |
| 文件頁數(shù)： | 20/107頁 |
| 文件大?。?/td> | 707K |
| 代理商： | TVP3026-220 |
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2–6
Table 2–5. Clock-Selection Register Bits CSR(6–4)
(Index: 0x1A, Access: R/W, Default: 0x07)
CLOCK-SELECT REGISTER BITS
VCLK FREQUENCY
6
0
5
0
4
0
Dot clock
0
0
1
Dot clock/2
0
1
0
Dot clock/4
0
1
1
1
0
0
1
0
1
Dot clock/8
Dot clock/16
Dot clock/32
1
1
0
Dot clock/64
1
1
1
Reset to 0
NOTE 2: Bit CSR7 enables the SCLK output when set to 1.
Table 2–6. Clock-Selection Register Bits CSR(3–0) (Index: 0x1A, Access: R/W, Default: 0x07)
CLOCK SELECT REGISTER BITS
3
2
0
0
FUNCTION
1
0
0
0
Select CLK0 as clock source (for use with LCLK latching of VGA port). See
subsection 2.6.2, VGA Modes
0
0
0
1
Select CLK1 as clock source
0
0
1
0
Select CLK2 as TTL clock source
0
0
0
0
1
1
1
0
0
1
0
1
Select CLK2 as TTL clock source
Select CLK2 and CLK2 as ECL clock source
Select pixel clock PLL as clock source
0
1
1
0
Disable internal dot clock for reduced power consumption.
0
1
1
1
Select CLK0 as clock source (for use with CLK0 latching of VGA port). See
subsection 2.6.2, VGA Modes
1
X
X
X
Reserved
x = do not care
2.4
In addition to externally supplied clock sources, the TVP3026 has three on-chip, fully programmable,
frequency-synthesis phase-locked loops (PLLs). The first PLL ,pixel clock, is intended for pixel clock
generation for frequencies up to the device limit. The second PLL ,MCLK, is provided for general system
clocking such as the system clock or memory clock, and the third PLL ,called the loop clock PLL, is useful
for synchronizing pixel data and latch timing by compensating for system loop delay.
PLL Clock Generators
The clock generators use a modified M over (N
×
2
P
) scheme to enable a wide range of precise frequencies.
(Appendix A provides a listing of all frequencies that can be synthesized and the register values for each.)
The advanced PLLs utilize an internal loop filter to provide maximum noise immunity and minimum jitter.
Except for the reference crystal or oscillator, no external components or adjustments are necessary. Each
PLL can be independently enabled or disabled for maximum system flexibility. Figure 2–1 illustrates the
TVP3026 PLL clocking scheme. The PLLs are programmed through a group of four registers in the
TVP3026 indirect register map. The registers are listed in Table 2–7.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TVP3026-220AMDN | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
| TVP3026-220APCE | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
| TVP3026-220BMDN | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
| TVP3026-220BPCE | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TVP3026-220MDN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC) |
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