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參數(shù)資料
| 型號： | PI7C9X7954AFDE |
| 廠商： | Pericom |
| 文件頁數(shù)： | 6/70頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PCIE-TO-UART BRIDGE 128LQFP |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 應(yīng)用： | PCIe至UART橋接 |
| 接口： | 高級配置電源接口（ACPI） |
| 電源電壓： | 1.8V, 3.3V |
| 封裝/外殼： | 128-LQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 128-LQFP（14x14） |
| 包裝： | 托盤 |
| 安裝類型： | 表面貼裝 |
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PI7C9X7954
PCI Express Quad UART
Datasheet
Page 14 of 70
May 2013 – Revision 1.4
Pericom Semiconductor
PIN NO.
NAME
TYPE
DESCRIPTION
*48, *47,
*46, *45,
*44, *43,
*39, *38
GPIO [7:0]
I/O
General-Purpose Bi-Direction Signals / SR_ORG: These eight
general-purpose pins are programmed as either input-only or
bi-directional pins by writing the GPIO output enable control
register. GPIO[2] is a bi-directional signal with a weak internal
pull-up resistor, and other GPIO pins are bi-directional signals with
weak internal pull-down resistors.
EEPROM Organization Pin (SR_ORG): During system
initialization, GPIO[7] acts as the SR_ORG pin, and it is used to
select the organization structure of the EEPROM. The pin is
active-high. When it is asserted at start-up, the EEPROM
configuration data is organized in 16-bit structure. Otherwise, 8-bit
structure is used.
Receiver Termination Adjustment (RXTERMADJ[1:0]): During
system initialization, GPIO[6:5] acts as the RXTERMADJ[1:0] pins,
and they are used to adjust the receive termination resistor value. By
default, they are set to ‘00’ without pin strapped.
Transmit Termination Adjustment (TXTERMADJ[1:0]): During
system initialization, GPIO[4:3] acts as the TXTERMADJ[1:0] pins,
and they are used to adjust the transmit termination resistor value.
By default, they are set to “00” without pin strapped.
Driver Equalization Level Control (DEQ[3:1]): During system
initialization, GPIO[2:0] acts as the DEQ[3:1] pins, and they are
used to control the driver current level. By default, they are set to
‘100’ without pin strapped.
14
WAKEUP_L
O
Wakeup Signal (Active LOW): When the Ring Indicator is
received on UART channel 0 in L2 state, the WAKEUP_L is
asserted. WAKEUP_L is an output signal with a weak internal
pull-down resistor.
4.2.4.
TEST SIGNALS
PIN NO.
NAME
TYPE
DESCRIPTION
106
JTG_TDI
I
Test Data Input: When SCAN_EN is high, the pin is used (in
conjunction with TCK) to shift data and instructions into the TAP in
a serial bit stream. JTG_TDI is an input signal with a weak internal
pull-up resistor.
109
JTG_TDO
O
Test Data Output: When SCAN_EN is high, it is used (in
conjunction with TCK) to shift data out of the Test Access Port
(TAP) in a serial bit stream
107
JTG_TMS
I
Test Mode Select: Used to control the state of the Test Access Port
controller. JTG_TMS is an input signal with a weak internal pull-up
resistor.
108
JTG_TCK
I
Test Clock: Used to clock state information and data into and out of
the chip during boundary scan.
110
JTG_TRST_L
I
Test Reset: Active LOW signal to reset the TAP controller into an
initialized state. JTG_TRST_L is an input signal with a weak
internal pull-up resistor.
5
SCAN_EN
I
Scan Test Enable Pin: SCAN_EN is an input signal with a weak
internal pull-up resistor.
37
TEST
I
This input signal should be tied to ground during normal operation.
97, 102, 103,
104, 105,
111, 112,
113, 114
NC
These pins can be left floating.
13-0093
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