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參數(shù)資料
| 型號(hào)： | PI7C9X7954AFDE |
| 廠商： | Pericom |
| 文件頁(yè)數(shù)： | 14/70頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC PCIE-TO-UART BRIDGE 128LQFP |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 應(yīng)用： | PCIe至UART橋接 |
| 接口： | 高級(jí)配置電源接口（ACPI） |
| 電源電壓： | 1.8V, 3.3V |
| 封裝/外殼： | 128-LQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 128-LQFP（14x14） |
| 包裝： | 托盤 |
| 安裝類型： | 表面貼裝 |
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PI7C9X7954
PCI Express Quad UART
Datasheet
Page 21 of 70
May 2013 – Revision 1.4
Pericom Semiconductor
5.2.9.
Automated Flow Control
The device uses automatic in-band flow control to prevent data-overrun to the local receive FIFO and
remote receive FIFO. This feature works in conjunction with the special character detection. When an
XOFF condition is detected, the UART transmitter will suspend any further data transmission after the
current character transmission is completed. The transmitter will resume data-transmission as soon as an
XON condition is detected. The automatic in-band feature is enabled by the Enhanced Function Register
(EFR). EFR[1:0] enables the in-band receive flow control, and EFR[3:2] enables the in-band transmit flow
control.
The out-of-band flow control utilizes RTS# and CTS# pins to suspend and resume the data transmission
and to prevent data-overrun. An asserted CTS# pin signals the UART to suspend transmission due to a full
remote receive FIFO. Upon detecting an asserted CTS# pin, the UART will complete the current character
transmission and enters idle mode until the CTS# pin is deasserted.
The UART deasserts RTS# to signal the remote transmitter that the local receive FIFO reaches the
programmed upper trigger level. When the local receive FIFO falls below the programmed lower trigger
level, the RTS# is reasserted. The automatic out-of-band flow control is enabled by EFR[7:6].
13-0093
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