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參數(shù)資料
| 型號(hào)： | PI7C9X7954AFDE |
| 廠商： | Pericom |
| 文件頁(yè)數(shù)： | 17/70頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC PCIE-TO-UART BRIDGE 128LQFP |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 應(yīng)用： | PCIe至UART橋接 |
| 接口： | 高級(jí)配置電源接口（ACPI） |
| 電源電壓： | 1.8V, 3.3V |
| 封裝/外殼： | 128-LQFP 裸露焊盤(pán) |
| 供應(yīng)商設(shè)備封裝： | 128-LQFP（14x14） |
| 包裝： | 托盤(pán) |
| 安裝類(lèi)型： | 表面貼裝 |
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PI7C9X7954
PCI Express Quad UART
Datasheet
Page 24 of 70
May 2013 – Revision 1.4
Pericom Semiconductor
escaler
Divisor
ency
InputFrequ
BaudRate
Pr
*
5.2.12. Baud Rate Generation
The built-in Baud Rate Generator (BRG) allows a wide range of input frequency and flexible Baud Rate
generation. To obtain the desired Baud Rate, the user can set the Sample Clock Register (SCR), Divisor
Latch Low Register (DLL), Divisor Latch High Register (DLH) and Clock Prescale Registers (CPRM and
CPRN). The Baud Rate is generated according to the following equation:
The parameters in the equation above can be programmed by setting the “SCR”, “DLL”, “DLH”, “CPRM”
and “CPRN” registers according to the table below.
Table 5-2 Baud Rate Generator Setting
Setting
Description
Divisor
DLL + (256 * DLH)
Prescaler
)
k
SampleCloc
(
*
2 1
N
M
SampleClock
SCR
16
,
(SCR = ‘0h’ to ‘Ch’)
M
CPRM, (CPRM = ‘01h’ to ‘02h’)
N
CPRN, (CPRN = ‘0h’ to ‘7h’)
To ensure the proper operation of the Baud Rate Generator, users should avoid setting the value ‘0’ to
Sample Clock, Divisor and Prescaler.
The following table lists some of the commonly used Baud Rates and the register settings that generate a
specific Baud Rate. The examples assume an Input Clock frequency of 14.7456 Mhz. The SCR register is
set to ‘0h’, and the CPRM and CPRN registers are set to ‘1h’ and ‘0h’ respectively. In these examples, the
Baud Rates can be generated by different combination of the DLH and DLL register values.
Table 5-3 Sample Baud Rate Setting
Baud Rate
DLH
DLL
1,200
3h
00h
2,400
1h
80h
4,800
0h
C0h
9,600
0h
60h
19,200
0h
30h
28,800
0h
20h
38,400
0h
18h
57,600
0h
10h
115,200
0h
08h
921,600
0h
01h
5.2.13. Power Management
The PI7C9X7954 supports the D0, D1, D2 and D3 power states. The device is compliant with PCI Power
Management Specification Revision 1.2.
13-0093
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