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PI7C9X7954
PCI Express Quad UART
Datasheet
Page 31 of 70
May 2013 – Revision 1.4
Pericom Semiconductor
6.2.24. MESSAGE SIGNALED INTERRUPTS (MSI) NEXT ITEM POINTER 8Ch
BIT
FUNCTION
TYPE
DESCRIPTION
15:8
Next Item Pointer
RO
The pointer points to the Vendor Specific capability register (9Ch).
Reset to 9Ch.
6.2.25.
MESSAGE ADDRESS REGISTER – OFFSET 90h
BIT
FUNCTION
TYPE
DESCRIPTION
1:0
Reserved
RO
Reset to 00b.
31:2
Message Address
RW
If the message enable bit is set, the contents of this register specify
the DWORD aligned address for MSI memory write transaction.
Reset to 0.
6.2.26.
MESSAGE UPPER ADDRESS REGISTER – OFFSET 94h
BIT
FUNCTION
TYPE
DESCRIPTION
31:0
Message Upper
Address
RW
This register is only effective if the device supports a 64-bit message
address is set.
Reset to 00000000h.
6.2.27.
MESSAGE DATA REGISTER – OFFSET 98h
BIT
FUNCTION
TYPE
DESCRIPTION
15:0
Message Data
RW
Reset to 0000h.
6.2.28. VPD CAPABILITY ID REGISTER – OFFSET 9Ch
BIT
FUNCTION
TYPE
DESCRIPTION
7:0
Enhanced
Capabilities ID
RO
Read as 03h to indicate that these are VPD enhanced capability
registers.
6.2.29. NEXT ITEM POINTER REGISTER – OFFSET 9Ch
BIT
FUNCTION
TYPE
DESCRIPTION
15:8
Next Item Pointer
RO
The pointer points to the VPD capability register (A4h).
Reset to A4h
6.2.30. VPD REGISTER – OFFSET 9Ch
BIT
FUNCTION
TYPE
DESCRIPTION
16
VPD Start
RW
Starts VPD read or write cycle. Assert by software and is
de-asserted by hardware.
Reset to 0b.
17
VPD Operation
RW
0b: Performs VPD read command to VPD table at the location as
specified in VPD address
1b: Performs VPD write command to VPD table at the location
as specified in VPD address
Reset to 0b.
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