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參數(shù)資料
| 型號： | PI7C9X7954AFDE |
| 廠商： | Pericom |
| 文件頁數(shù)： | 30/70頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PCIE-TO-UART BRIDGE 128LQFP |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 應(yīng)用： | PCIe至UART橋接 |
| 接口： | 高級配置電源接口（ACPI） |
| 電源電壓： | 1.8V, 3.3V |
| 封裝/外殼： | 128-LQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 128-LQFP（14x14） |
| 包裝： | 托盤 |
| 安裝類型： | 表面貼裝 |
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PI7C9X7954
PCI Express Quad UART
Datasheet
Page 36 of 70
May 2013 – Revision 1.4
Pericom Semiconductor
6.2.50. DEVICE CAPABILITIES REGISTER – OFFSET E4h
BIT
FUNCTION
TYPE
DESCRIPTION
2:0
Max_Payload_Size
Supported
RO
Indicates the maximum payload size that the I/O bridge can support
for TLPs. The I/O bridge supports 128 bytes max payload size.
Reset to000b.
4:3
Phantom Functions
Supported
RO
It is not implemented. Hardwired to 00b.
5
Extended Tag Field
Supported
RO
It is not implemented. Hardwired to 0b.
8:6
Endpoint L0s
Acceptable Latency
RO
Acceptable total latency that an Endpoint can withstand due to the
transition from L0s state to the L0 state.
Reset to 000b.
11:9
Endpoint L1
Acceptable Latency
RO
Acceptable total latency that an Endpoint can withstand due to the
transition from L1 state to the L0 state.
Reset to 000b.
12
Attention Button
Present
RO
It is not implemented. Hardwired to 0b.
13
Attention Indicator
Present
RO
It is not implemented. Hardwired to 0b.
14
Power Indicator
Present
RO
It is not implemented. Hardwired to 0b.
15
Role_Base Error
Reporting
RO
When set, indicated that the device implements the functionality
originally defined in the Error Reporting ECN. The default value
may be changed by auto-loading from EEPROM.
Reset to 1b.
17:16
Reserved
RO
Reset to 00b.
25:18
Captured Slot Power
Limit Value
RO
In combination with the Slot Power Limit Scale value, specifies the
upper limit on power supplied by slot.
This value is set by the Set_Slot_Power_Limit message or
hardwired to “00h”.
Reset to 00b.
27:26
Captured Slot Power
Limit Scale
RO
Specifies the scale used for the Slot Power Limit Value.
This value is set by the Set_Slot_Power_Limit message or
hardwired to “00b”.
Reset to 00b.
31:28
Reserved
RO
Reset to 0h.
6.2.51. DEVICE CONTROL REGISTER – OFFSET E8h
BIT
FUNCTION
TYPE
DESCRIPTION
0
Correctable Error
Reporting Enable
RW
0b: Disable Correctable Error Reporting.
1b: Enable Correctable Error Reporting.
Reset to 0b.
1
Non-Fatal Error
Reporting Enable
RW
0b: Disable Non-Fatal Error Reporting.
1b: Enable Non-Fatal Error Reporting.
Reset to 0b.
2
Fatal Error
Reporting Enable
RW
0b: Disable Fatal Error Reporting.
1b: Enable Fatal Error Reporting.
Reset to 0b.
13-0093
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