Pericom Semiconductor Table of Contents 1. FEATURES ..........." />
參數(shù)資料
型號(hào)： PI7C9X7954AFDE
廠商： Pericom
文件頁(yè)數(shù)： 34/70頁(yè)
文件大小： 0K
描述： IC PCIE-TO-UART BRIDGE 128LQFP
標(biāo)準(zhǔn)包裝： 90
應(yīng)用： PCIe至UART橋接
接口： 高級(jí)配置電源接口（ACPI）
電源電壓： 1.8V, 3.3V
封裝/外殼： 128-LQFP 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 128-LQFP（14x14）
包裝： 托盤(pán)
安裝類(lèi)型： 表面貼裝
PI7C9X7954
PCI Express Quad UART
Datasheet
Page 4 of 70
May 2013 – Revision 1.4
Pericom Semiconductor
Table of Contents
1.
FEATURES ............................................................................................................................................9
2.
APPLICATIONS ...................................................................................................................................9
3.
GENERAL DESCRIPTION ...............................................................................................................10
4.
PIN ASSIGNMENT.............................................................................................................................11
4.1.
PIN LIST OF 128-PIN LQFP..........................................................................................................11
4.2.
PIN DESCRIPTION ......................................................................................................................12
4.2.1.
UART INTERFACE................................................................................................................12
4.2.2.
PCI EXPRESS INTERFACE ..................................................................................................13
4.2.3.
SYSTEM INTERFACE............................................................................................................13
4.2.4.
TEST SIGNALS......................................................................................................................14
4.2.5.
EEPROM INTERFACE..........................................................................................................15
4.2.6.
POWER PINS ........................................................................................................................16
5.
FUNCTIONAL DESCRIPTION ........................................................................................................17
5.1.
CONFIGURATION SPACE ..........................................................................................................17
5.1.1.
PCI Express Configuration Space .........................................................................................17
5.1.2.
UART Configuration Space ...................................................................................................17
5.2.
DEVICE OPERATION..................................................................................................................18
5.2.1.
Configuration Access.............................................................................................................18
5.2.2.
I/O Reads/Writes....................................................................................................................18
5.2.3.
Memory Reads/Writes ............................................................................................................18
5.2.4.
Mode Selection ......................................................................................................................19
5.2.5.
450/550 Mode ........................................................................................................................19
5.2.6.
Enhanced 550 Mode ..............................................................................................................19
5.2.7.
Enhanced 950 Mode ..............................................................................................................19
5.2.8.
Transmit and Receive FIFOs .................................................................................................19
5.2.9.
Automated Flow Control........................................................................................................21
5.2.10.
Internal Loopback..................................................................................................................22
5.2.11.
Crystal Oscillator ..................................................................................................................23
5.2.12.
Baud Rate Generation ...........................................................................................................24
5.2.13.
Power Management ...............................................................................................................24
6.
PCI EXPRESS REGISTER DESCRIPTION ...................................................................................25
6.1.
REGISTER TYPES .......................................................................................................................25
6.2.
CONFIGURATION REGISTERS.................................................................................................25
6.2.1.
VENDOR ID REGISTER – OFFSET 00h ..............................................................................26
6.2.2.
DEVICE ID REGISTER – OFFSET 00h................................................................................26
6.2.3.
COMMAND REGISTER – OFFSET 04h...............................................................................26
6.2.4.
STATUS REGISTER – OFFSET 04h......................................................................................27
6.2.5.
REVISION ID REGISTER – OFFSET 08h ............................................................................27
6.2.6.
CLASS CODE REGISTER – OFFSET 08h............................................................................27
6.2.7.
CACHE LINE REGISTER – OFFSET 0Ch............................................................................28
6.2.8.
MASTER LATENCY TIMER REGISTER – OFFSET 0Ch .....................................................28
6.2.9.
HEADER TYPE REGISTER – OFFSET 0Ch.........................................................................28
6.2.10.
BASE ADDRESS REGISTER 0 – OFFSET 10h.....................................................................28
6.2.11.
BASE ADDRESS REGISTER 1 – OFFSET 14h.....................................................................28
6.2.12.
SUBSYSTEM VENDOR REGISTER – OFFSET 2Ch ............................................................28
6.2.13.
SUBSYSTEM ID REGISTER – OFFSET 2Ch........................................................................28
13-0093
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