參數資料
| 型號： | PI7C9X7954AFDE |
| 廠商： | Pericom |
| 文件頁數： | 24/70頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PCIE-TO-UART BRIDGE 128LQFP |
| 標準包裝： | 90 |
| 應用： | PCIe至UART橋接 |
| 接口： | 高級配置電源接口（ACPI） |
| 電源電壓： | 1.8V, 3.3V |
| 封裝/外殼： | 128-LQFP 裸露焊盤 |
| 供應商設備封裝： | 128-LQFP（14x14） |
| 包裝： | 托盤 |
| 安裝類型： | 表面貼裝 |
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PI7C9X7954
PCI Express Quad UART
Datasheet
Page 30 of 70
May 2013 – Revision 1.4
Pericom Semiconductor
BIT
FUNCTION
TYPE
DESCRIPTION
31:27
PME# Support
RO
Read as 01000b to indicate the I/O bridge supports the forwarding of
PME# message in all power states. The default value may be
changed by auto-loading from EEPROM.
6.2.20. POWER MANAGEMENT DATA REGISTER – OFFSET 84h
BIT
FUNCTION
TYPE
DESCRIPTION
1:0
Power State
RW
Indicates the current power state of the I/O bridge. Writing a value of
D0 causes a hot reset without asserting PEREST_L when the
previous state was D3.
00b: D0 state
01b: D1 state
10b: D2 state
11b: D3 hot state
Reset to 00b.
2
Reserved
RO
Read as 0b.
3
No_Soft_Reset
RO
When set, this bit indicates that I/O bridge transitioning from D3hot
to D0 does not perform an internal reset.
When clear, an internal reset is performed when power state transits
from D3hot to D0. The default value may be changed by
auto-loading from EEPROM.
Reset to 0b.
7:4
Reserved
RO
Read as 0h.
8
PME# Enable
RW
When asserted, the I/O bridge will generate the PME# message.
Reset to 0b.
12:9
Data Select
RW
Select data registers.
Reset to 0h.
14:13
Data Scale
RO
Read as 00b.
15
PME status
RO
Indicates that the PME# message is pending internally to the I/O
bridge.
Reset to 0b.
6.2.21. PPB SUPPORT EXTENSIONS – OFFSET 84h
BIT
FUNCTION
TYPE
DESCRIPTION
21:16
Reserved
RO
Reset to 000000b.
22
B2_B3 Support for
D3HOT
RO
Does not apply to PCI Express. Must be hardwired to 0b.
23
Bus Power / Clock
Control Enable
RO
Does not apply to PCI Express. Must be hardwired to 0b.
6.2.22. PM DATA REGISTER – OFFSET 84h
BIT
FUNCTION
TYPE
DESCRIPTION
31:24
PM Data Register
RO
PM Data Register.
Reset to 00h
6.2.23. MESSAGE SIGNALED INTERRUPTS (MSI) Capability ID Register 8Ch
BIT
FUNCTION
TYPE
DESCRIPTION
7:0
Enhanced
Capability ID
RO
Read as 05h to indicate that this is Message Signaled Interrupt
capability register.
13-0093
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