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參數(shù)資料
| 型號(hào)： | PI7C9X7954AFDE |
| 廠商： | Pericom |
| 文件頁數(shù)： | 10/70頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PCIE-TO-UART BRIDGE 128LQFP |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 應(yīng)用： | PCIe至UART橋接 |
| 接口： | 高級(jí)配置電源接口（ACPI） |
| 電源電壓： | 1.8V, 3.3V |
| 封裝/外殼： | 128-LQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 128-LQFP（14x14） |
| 包裝： | 托盤 |
| 安裝類型： | 表面貼裝 |
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PI7C9X7954
PCI Express Quad UART
Datasheet
Page 18 of 70
May 2013 – Revision 1.4
Pericom Semiconductor
of the UART blocks are offset by the base address referred by the Base Address Register (BAR). The value
of the base address is loaded from the I/O or Memory Base Address defined in the PCI Express
configuration space.
The PI7C9X7954 also supports enhanced features such as Xon/Xoff, automatic flow control, Baud Rate
prescaling and various status monitoring. These enhanced features are available through the memory
address offset by the BAR in the PCI Express configuration space.
The basic features available in the registers in I/O mode are also available in the registers in
memory-mapping mode. Accesses to these registers are equivalent in these two modes.
The UARTs on the PI7C9X7954 supports operations in 16C450, 16C550 and 16C950 modes. These modes
of operation are selected by writing the SFR, FCR and EFR registers. The PI7C9X7954 is backward
compatible with these modes of operation.
5.2. DEVICE OPERATION
The PI7C9X7954 is configured by the Root Complex in the bootstrap process during system start-up. The
Root Complex performs bus scans and recognizes the device by reading vendor and device IDs. Upon
successful device identification, the system then loads device-specific driver software and allocates I/O,
memory and interrupt resources. The driver software allows the user to access the functions of the device
by reading and writing the UART registers. The PCI Express interface incorporates convenient device
operation and high system performance.
5.2.1.
Configuration Access
The PI7C9X7954 accepts type 0 configuration read and write accesses defined in the PCI Express Base1.1
Specification. The first 256 bytes of the PCI Express configuration are compatible with PCI 3.0.
5.2.2.
I/O Reads/Writes
The PCI Express interface of the PI7C9X7954 decodes incoming transaction packets. If the address is
within the region assigned by the I/O Base Address Registers, the transaction is recognized as an I/O Read
or Write.
5.2.3.
Memory Reads/Writes
Similar to the I/O Read/Write, if the address of the transaction packet is within the memory range, a
Memory Read/Write occurs.
13-0093
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