Pericom Semiconductor 7. UART REGISTER DESCRIPTION............." />
參數(shù)資料
型號(hào)： PI7C9X7954AFDE
廠商： Pericom
文件頁(yè)數(shù)： 56/70頁(yè)
文件大小： 0K
描述： IC PCIE-TO-UART BRIDGE 128LQFP
標(biāo)準(zhǔn)包裝： 90
應(yīng)用： PCIe至UART橋接
接口： 高級(jí)配置電源接口（ACPI）
電源電壓： 1.8V, 3.3V
封裝/外殼： 128-LQFP 裸露焊盤
供應(yīng)商設(shè)備封裝： 128-LQFP（14x14）
包裝： 托盤
安裝類型： 表面貼裝
PI7C9X7954
PCI Express Quad UART
Datasheet
Page 6 of 70
May 2013 – Revision 1.4
Pericom Semiconductor
7.
UART REGISTER DESCRIPTION..................................................................................................44
7.1.
REGISTERS IN I/O MODE ..........................................................................................................44
7.1.1.
RECEIVE HOLDING REGISTER – OFFSET 00h ................................................................45
7.1.2.
TRANSMIT HOLDING REGISTER – OFFSET 00h..............................................................45
7.1.3.
INTERRUPT ENABLE REGISTER – OFFSET 01h ..............................................................45
7.1.4.
INTERRUPT STATUS REGISTER – OFFSET 02h................................................................46
7.1.5.
FIFO CONTROL REGISTER – OFFSET 02h .......................................................................46
7.1.6.
LINE CONTROL REGISTER – OFFSET 03h .......................................................................46
7.1.7.
MODEM CONTROL REGISTER – OFFSET 04h .................................................................47
7.1.8.
LINE STATUS REGISTER – OFFSET 05h ............................................................................48
7.1.9.
MODEM STATUS REGISTER – OFFSET 06h......................................................................49
7.1.10.
SPECIAL FUNCTION REGISTER – OFFSET 07h...............................................................49
7.1.11.
DIVISOR LATCH LOW REGISTER – OFFSET 00h, LCR[7] = 1 ........................................50
7.1.12.
DIVISOR LATCH HIGH REGISTER – OFFSET 01h, LCR[7] = 1.......................................50
7.1.13.
SAMPLE CLOCK REGISTER – OFFSET 02h, LCR[7] = 1 .................................................50
7.2.
REGISTERS IN MEMORY-MAPPING MODE.......................................................................................51
7.2.1.
RECEIVE HOLDING REGISTER – OFFSET 00h ................................................................52
7.2.2.
TRANSMIT HOLDING REGISTER – OFFSET 00h..............................................................53
7.2.3.
INTERRUPT ENABLE REGISTER – OFFSET 01h ..............................................................53
7.2.4.
INTERRUPT STATUS REGISTER – OFFSET 02h................................................................53
7.2.5.
FIFO CONTROL REGISTER – OFFSET 02h .......................................................................54
7.2.6.
LINE CONTROL REGISTER – OFFSET 03h .......................................................................54
7.2.7.
MODEM CONTROL REGISTER – OFFSET 04h .................................................................55
7.2.8.
LINE STATUS REGISTER – OFFSET 05h ............................................................................56
7.2.9.
MODEM STATUS REGISTER – OFFSET 06h......................................................................56
7.2.10.
SPECIAL FUNCTION REGISTER – OFFSET 07h...............................................................57
7.2.11.
DIVISOR LATCH LOW REGISTER – OFFSET 08h .............................................................57
7.2.12.
DIVISOR LATCH HIGH REGISTER – OFFSET 09h............................................................57
7.2.13.
ENHANCED FUNCTION REGISTER – OFFSET 0Ah.........................................................57
7.2.14.
XON SPECIAL CHARACTER 1 – OFFSET 0Bh...................................................................59
7.2.15.
XON SPECIAL CHARACTER 2 – OFFSET 0Ch ..................................................................59
7.2.16.
XOFF SPECIAL CHARACTER 1 – OFFSET 0Dh ................................................................59
7.2.17.
XOFF SPECIAL CHARACTER 2 – OFFSET 0Eh ................................................................59
7.2.18.
ADVANCE CONTROL REGISTER – OFFSET 0Fh ..............................................................59
7.2.19.
TRANSMIT INTERRUPT TRIGGER LEVEL – OFFSET 10h................................................60
7.2.20.
RECEIVE INTERRUPT TRIGGER LEVEL – OFFSET 11h ..................................................60
7.2.21.
FLOW CONTROL LOW TRIGGER LEVEL – OFFSET 12h .................................................60
7.2.22.
FLOW CONTROL HIGH TRIGGER LEVEL – OFFSET 13h ...............................................60
7.2.23.
CLOCK PRESCALE REGISTER – OFFSET 14h..................................................................60
7.2.24.
RECEIVE FIFO DATA COUNTER – OFFSET 15h, SFR[6] = 0..........................................60
7.2.25.
LINE STATUS REGISTER COUNTER – OFFSET 15h, SFR[6] = 1 ....................................61
7.2.26.
TRANSMIT FIFO DATA COUNTER – OFFSET 16h, SFR[7] = 1 .......................................61
7.2.27.
SAMPLE CLOCK REGISTER – OFFSET 16h, SFR[7] = 0 .................................................61
7.2.28.
GLOBAL LINE STATUS REGISTER – OFFSET 17h ............................................................61
7.2.29.
RECEIVE FIFO DATA REGISTERS – OFFSET 100h ~ 17Fh..............................................62
7.2.30.
TRANSMIT FIFO DATA REGISTERS – OFFSET 100h ~ 17Fh ...........................................62
7.2.31.
LINE STATUS FIFO REGISTERS –OFFSET 180h ~ 1FFh ..................................................62
8.
EEPROM INTERFACE .....................................................................................................................63
8.1.
AUTO MODE EERPOM ACCESS ...............................................................................................63
8.2.
EEPROM MODE AT RESET ........................................................................................................63
8.3.
EEPROM SPACE ADDRESS MAP AND DESCRIPTION ..........................................................63
13-0093
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