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PI7C9X7954
PCI Express Quad UART
Datasheet
Page 25 of 70
May 2013 – Revision 1.4
Pericom Semiconductor
6. PCI EXPRESS REGISTER DESCRIPTION
6.1. REGISTER TYPES
REGISTER TYPE
DEFINITION
HwInt
Hardware Initialization
RO
Read Only
WO
Write Only
RW
Read / Write
RWC
Read / Write 1 to Clear
RWCS
Sticky - Read Only / Write 1 to Clear
RWS
Sticky - Read / Write
6.2. CONFIGURATION REGISTERS
The following table details the allocation of the register fields of the PCI 2.3 compatible type
0 configuration space header.
31 – 24
23 – 16
15 – 8
7 – 0
BYTE OFFSET
Device ID
Vendor ID
00h
Status
Command
04h
Class Code
Revision ID
08h
Reserved
Header Type
Master Latency
Timer
Cache Line Size
0Ch
Base Address Register 0
10h
Base Address Register 1
14h
Reserved
18h~28h
Subsystem ID
Subsystem Vendor ID
2Ch
Reserved
30h
Capability Pointer
34h
Reserved
38h
Reserved
Interrupt Pin
Interrupt Line
3Ch
Reserved
40h – 7Fh
Power Management Capabilities
Next ID = 8C
Capability ID = 01
80h
PM Data
PPB Support
Power Management Data
84h
Message Control Register
Next ID =9C
Capability ID = 05
8Ch
Message Address Register
90h
Message Upper Address Register
94h
Message Data Register
98h
VPD Register
Next ID = A4
Capability ID = 03
9Ch
VPD Data Register
A0h
Vendor Define Register(28h)
Next ID = E0
Capability ID = 09
A4h
XPIP CSR0
A8h
XPIP CSR1
Ach
ACK Latency Timer
Replay Time-out counter
B0h
UART Driver Selection
B4h
Power Management Control Parameter
B8h
Debug Register
BCh – C4h
PHY Parameter
C8h
Reserved
CCh – D4h
GPIO Data and Control
D8h
EEPROM Data
EEPROM Control
DCh
PCI Express Capability Register
Next ID = 00h
Capability ID = 10
E0h
Device Capability
E4h
Device Status
Device Control
E8h
Link Capability
ECh
Link Status
Link Control
F0h
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