Pericom Semiconductor BIT FUNCTION TYPE DESCRIPTION 15:8 GPIO " />
參數(shù)資料
型號(hào): PI7C9X7954AFDE
廠商: Pericom
文件頁(yè)數(shù): 29/70頁(yè)
文件大?。?/td> 0K
描述: IC PCIE-TO-UART BRIDGE 128LQFP
標(biāo)準(zhǔn)包裝: 90
應(yīng)用: PCIe至UART橋接
接口: 高級(jí)配置電源接口(ACPI)
電源電壓: 1.8V, 3.3V
封裝/外殼: 128-LQFP 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝: 128-LQFP(14x14)
包裝: 托盤(pán)
安裝類型: 表面貼裝
PI7C9X7954
PCI Express Quad UART
Datasheet
Page 35 of 70
May 2013 – Revision 1.4
Pericom Semiconductor
BIT
FUNCTION
TYPE
DESCRIPTION
15:8
GPIO I/O Enable
RW
These 8 bits determine whether the GPIO pins are input or output
pins. Bit[x+8] corresponds to GPIO[x], where x=7 to 0. If the bit is
set to “0”, the corresponding GPIO pin is an input pin. If the bit is set
to “1”, the corresponding GPIO pin is an output pin.
23:16
GPIO Output
RW
The current state of the GPIO[x] pin can be written by bit[x+16] in
this register, where x=7 to 0. The bits are effective only when the
corresponding GPIO I/O Enable bits are set to “1”.
31:24
Reserved
RO
Reserved
6.2.46. EEPROM CONTROL REGISTER – OFFSET DCh
BIT
FUNCTION
TYPE
DESCRIPTION
0
EEPROM Start
RW
Starts the EEPROM read or write cycle.
Reset to 0b.
1
Reserved
RO
Reset to 0b.
2
EEPROM Preload
Control
RW
Enable preload start.
Reset to 0b.
4:3
EEPROM
Operation
Command
RW
EEPROM Operation Command.
00b: Reserved
01b: Write operation command
10b: Read operation command
11b: Reserved
Reset to 00b.
15:5
EEPROM Address
RW
EEPROM RW address.
Reset to 000h.
31:16
EEPROM Write
DATA Buffer
RW
EEPROM write data buffer register.
Reset to 0000h.
6.2.47. PCI EXPRESS CAPABILITY ID REGISTER – OFFSET E0h
BIT
FUNCTION
TYPE
DESCRIPTION
7:0
Enhanced
Capabilities ID
RO
Read as 10h to indicate that these are PCI express enhanced
capability registers.
6.2.48. NEXT ITEM POINTER REGISTER – OFFSET E0h
BIT
FUNCTION
TYPE
DESCRIPTION
15:8
Next Item Pointer
RO
Read as 00h. No other ECP registers.
Reset to 00h.
6.2.49. PCI EXPRESS CAPABILITIES REGISTER – OFFSET E0h
BIT
FUNCTION
TYPE
DESCRIPTION
19:16
Capability Version
RO
Read as 0001b to indicate the I/O bridge is compliant to Revision
1.0a of PCI Express Base Specifications.
23:20
Device/Port Type
RO
Indicates the type of Legacy PCI Express Endpoint device.
Reset to 1h.
24
Slot Implemented
RO
It is not implemented. Hardwired to 0b.
29:25
Interrupt Message
Number
RO
It is not implemented. Hardwired to 00000b.
31:30
Reserved
RO
Reset to 00b.
13-0093
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